1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#include "arch/kernel_stats.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/checker/thread_context.hh"
51#include "cpu/o3/cpu.hh"
52#include "cpu/o3/isa_specific.hh"
53#include "cpu/o3/thread_context.hh"
54#include "cpu/activity.hh"
55#include "cpu/quiesce_event.hh"
56#include "cpu/simple_thread.hh"
57#include "cpu/thread_context.hh"
58#include "debug/Activity.hh"
59#include "debug/Drain.hh"
60#include "debug/O3CPU.hh"
61#include "debug/Quiesce.hh"
62#include "enums/MemoryMode.hh"
63#include "sim/core.hh"
64#include "sim/full_system.hh"
65#include "sim/process.hh"
66#include "sim/stat_control.hh"
67#include "sim/system.hh"
68
69#if THE_ISA == ALPHA_ISA
70#include "arch/alpha/osfpal.hh"
71#include "debug/Activity.hh"
72#endif
73
74struct BaseCPUParams;
75
76using namespace TheISA;
77using namespace std;
78
79BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
80 : BaseCPU(params)
81{
82}
83
84void
85BaseO3CPU::regStats()
86{
87 BaseCPU::regStats();
88}
89
90template<class Impl>
91bool
92FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
93{
94 DPRINTF(O3CPU, "Fetch unit received timing\n");
95 // We shouldn't ever get a block in ownership state
96 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
97 fetch->processCacheCompletion(pkt);
98
99 return true;
100}
101
102template<class Impl>
103void
104FullO3CPU<Impl>::IcachePort::recvRetry()
105{
106 fetch->recvRetry();
107}
108
109template <class Impl>
110bool
111FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
112{
113 return lsq->recvTimingResp(pkt);
114}
115
116template <class Impl>
117void
118FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
119{
120 lsq->recvTimingSnoopReq(pkt);
121}
122
123template <class Impl>
124void
125FullO3CPU<Impl>::DcachePort::recvRetry()
126{
127 lsq->recvRetry();
128}
129
130template <class Impl>
131FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
132 : Event(CPU_Tick_Pri), cpu(c)
133{
134}
135
136template <class Impl>
137void
138FullO3CPU<Impl>::TickEvent::process()
139{
140 cpu->tick();
141}
142
143template <class Impl>
144const char *
145FullO3CPU<Impl>::TickEvent::description() const
146{
147 return "FullO3CPU tick";
148}
149
150template <class Impl>
151FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
152 : BaseO3CPU(params),
153 itb(params->itb),
154 dtb(params->dtb),
155 tickEvent(this),
156#ifndef NDEBUG
157 instcount(0),
158#endif
159 removeInstsThisCycle(false),
160 fetch(this, params),
161 decode(this, params),
162 rename(this, params),
163 iew(this, params),
164 commit(this, params),
165
166 regFile(params->numPhysIntRegs,
167 params->numPhysFloatRegs,
168 params->numPhysCCRegs),
169
170 freeList(name() + ".freelist", ®File),
171
172 rob(this, params),
173
174 scoreboard(name() + ".scoreboard",
175 regFile.totalNumPhysRegs(), TheISA::NumMiscRegs,
176 TheISA::ZeroReg, TheISA::ZeroReg),
177
178 isa(numThreads, NULL),
179
180 icachePort(&fetch, this),
181 dcachePort(&iew.ldstQueue, this),
182
183 timeBuffer(params->backComSize, params->forwardComSize),
184 fetchQueue(params->backComSize, params->forwardComSize),
185 decodeQueue(params->backComSize, params->forwardComSize),
186 renameQueue(params->backComSize, params->forwardComSize),
187 iewQueue(params->backComSize, params->forwardComSize),
188 activityRec(name(), NumStages,
189 params->backComSize + params->forwardComSize,
190 params->activity),
191
192 globalSeqNum(1),
193 system(params->system),
194 drainManager(NULL),
195 lastRunningCycle(curCycle())
196{
197 if (!params->switched_out) {
198 _status = Running;
199 } else {
200 _status = SwitchedOut;
201 }
202
203 if (params->checker) {
204 BaseCPU *temp_checker = params->checker;
205 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
206 checker->setIcachePort(&icachePort);
207 checker->setSystem(params->system);
208 } else {
209 checker = NULL;
210 }
211
212 if (!FullSystem) {
213 thread.resize(numThreads);
214 tids.resize(numThreads);
215 }
216
217 // The stages also need their CPU pointer setup. However this
218 // must be done at the upper level CPU because they have pointers
219 // to the upper level CPU, and not this FullO3CPU.
220
221 // Set up Pointers to the activeThreads list for each stage
222 fetch.setActiveThreads(&activeThreads);
223 decode.setActiveThreads(&activeThreads);
224 rename.setActiveThreads(&activeThreads);
225 iew.setActiveThreads(&activeThreads);
226 commit.setActiveThreads(&activeThreads);
227
228 // Give each of the stages the time buffer they will use.
229 fetch.setTimeBuffer(&timeBuffer);
230 decode.setTimeBuffer(&timeBuffer);
231 rename.setTimeBuffer(&timeBuffer);
232 iew.setTimeBuffer(&timeBuffer);
233 commit.setTimeBuffer(&timeBuffer);
234
235 // Also setup each of the stages' queues.
236 fetch.setFetchQueue(&fetchQueue);
237 decode.setFetchQueue(&fetchQueue);
238 commit.setFetchQueue(&fetchQueue);
239 decode.setDecodeQueue(&decodeQueue);
240 rename.setDecodeQueue(&decodeQueue);
241 rename.setRenameQueue(&renameQueue);
242 iew.setRenameQueue(&renameQueue);
243 iew.setIEWQueue(&iewQueue);
244 commit.setIEWQueue(&iewQueue);
245 commit.setRenameQueue(&renameQueue);
246
247 commit.setIEWStage(&iew);
248 rename.setIEWStage(&iew);
249 rename.setCommitStage(&commit);
250
251 ThreadID active_threads;
252 if (FullSystem) {
253 active_threads = 1;
254 } else {
255 active_threads = params->workload.size();
256
257 if (active_threads > Impl::MaxThreads) {
258 panic("Workload Size too large. Increase the 'MaxThreads' "
259 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
260 "or edit your workload size.");
261 }
262 }
263
264 //Make Sure That this a Valid Architeture
265 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
266 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
267 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
268
269 rename.setScoreboard(&scoreboard);
270 iew.setScoreboard(&scoreboard);
271
272 // Setup the rename map for whichever stages need it.
273 for (ThreadID tid = 0; tid < numThreads; tid++) {
274 isa[tid] = params->isa[tid];
275
276 // Only Alpha has an FP zero register, so for other ISAs we
277 // use an invalid FP register index to avoid special treatment
278 // of any valid FP reg.
279 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
280 RegIndex fpZeroReg =
281 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
282
283 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
284 &freeList);
285
286 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
287 &freeList);
288 }
289
290 // Initialize rename map to assign physical registers to the
291 // architectural registers for active threads only.
292 for (ThreadID tid = 0; tid < active_threads; tid++) {
293 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
294 // Note that we can't use the rename() method because we don't
295 // want special treatment for the zero register at this point
296 PhysRegIndex phys_reg = freeList.getIntReg();
297 renameMap[tid].setIntEntry(ridx, phys_reg);
298 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
299 }
300
301 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
302 PhysRegIndex phys_reg = freeList.getFloatReg();
303 renameMap[tid].setFloatEntry(ridx, phys_reg);
304 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
305 }
306
307 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
308 PhysRegIndex phys_reg = freeList.getCCReg();
309 renameMap[tid].setCCEntry(ridx, phys_reg);
310 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
311 }
312 }
313
314 rename.setRenameMap(renameMap);
315 commit.setRenameMap(commitRenameMap);
316 rename.setFreeList(&freeList);
317
318 // Setup the ROB for whichever stages need it.
319 commit.setROB(&rob);
320
321 lastActivatedCycle = 0;
322#if 0
323 // Give renameMap & rename stage access to the freeList;
324 for (ThreadID tid = 0; tid < numThreads; tid++)
325 globalSeqNum[tid] = 1;
326#endif
327
328 DPRINTF(O3CPU, "Creating O3CPU object.\n");
329
330 // Setup any thread state.
331 this->thread.resize(this->numThreads);
332
333 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
334 if (FullSystem) {
335 // SMT is not supported in FS mode yet.
336 assert(this->numThreads == 1);
337 this->thread[tid] = new Thread(this, 0, NULL);
338 } else {
339 if (tid < params->workload.size()) {
340 DPRINTF(O3CPU, "Workload[%i] process is %#x",
341 tid, this->thread[tid]);
342 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
343 (typename Impl::O3CPU *)(this),
344 tid, params->workload[tid]);
345
346 //usedTids[tid] = true;
347 //threadMap[tid] = tid;
348 } else {
349 //Allocate Empty thread so M5 can use later
350 //when scheduling threads to CPU
351 Process* dummy_proc = NULL;
352
353 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
354 (typename Impl::O3CPU *)(this),
355 tid, dummy_proc);
356 //usedTids[tid] = false;
357 }
358 }
359
360 ThreadContext *tc;
361
362 // Setup the TC that will serve as the interface to the threads/CPU.
363 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
364
365 tc = o3_tc;
366
367 // If we're using a checker, then the TC should be the
368 // CheckerThreadContext.
369 if (params->checker) {
370 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
371 o3_tc, this->checker);
372 }
373
374 o3_tc->cpu = (typename Impl::O3CPU *)(this);
375 assert(o3_tc->cpu);
376 o3_tc->thread = this->thread[tid];
377
378 if (FullSystem) {
379 // Setup quiesce event.
380 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
381 }
382 // Give the thread the TC.
383 this->thread[tid]->tc = tc;
384
385 // Add the TC to the CPU's list of TC's.
386 this->threadContexts.push_back(tc);
387 }
388
389 // FullO3CPU always requires an interrupt controller.
390 if (!params->switched_out && !interrupts) {
391 fatal("FullO3CPU %s has no interrupt controller.\n"
392 "Ensure createInterruptController() is called.\n", name());
393 }
394
395 for (ThreadID tid = 0; tid < this->numThreads; tid++)
396 this->thread[tid]->setFuncExeInst(0);
397}
398
399template <class Impl>
400FullO3CPU<Impl>::~FullO3CPU()
401{
402}
403
404template <class Impl>
405void
406FullO3CPU<Impl>::regProbePoints()
407{
408 BaseCPU::regProbePoints();
409
410 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
411 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
412
413 fetch.regProbePoints();
414 iew.regProbePoints();
415 commit.regProbePoints();
416}
417
418template <class Impl>
419void
420FullO3CPU<Impl>::regStats()
421{
422 BaseO3CPU::regStats();
423
424 // Register any of the O3CPU's stats here.
425 timesIdled
426 .name(name() + ".timesIdled")
427 .desc("Number of times that the entire CPU went into an idle state and"
428 " unscheduled itself")
429 .prereq(timesIdled);
430
431 idleCycles
432 .name(name() + ".idleCycles")
433 .desc("Total number of cycles that the CPU has spent unscheduled due "
434 "to idling")
435 .prereq(idleCycles);
436
437 quiesceCycles
438 .name(name() + ".quiesceCycles")
439 .desc("Total number of cycles that CPU has spent quiesced or waiting "
440 "for an interrupt")
441 .prereq(quiesceCycles);
442
443 // Number of Instructions simulated
444 // --------------------------------
445 // Should probably be in Base CPU but need templated
446 // MaxThreads so put in here instead
447 committedInsts
448 .init(numThreads)
449 .name(name() + ".committedInsts")
450 .desc("Number of Instructions Simulated")
451 .flags(Stats::total);
452
453 committedOps
454 .init(numThreads)
455 .name(name() + ".committedOps")
456 .desc("Number of Ops (including micro ops) Simulated")
457 .flags(Stats::total);
458
459 cpi
460 .name(name() + ".cpi")
461 .desc("CPI: Cycles Per Instruction")
462 .precision(6);
463 cpi = numCycles / committedInsts;
464
465 totalCpi
466 .name(name() + ".cpi_total")
467 .desc("CPI: Total CPI of All Threads")
468 .precision(6);
469 totalCpi = numCycles / sum(committedInsts);
470
471 ipc
472 .name(name() + ".ipc")
473 .desc("IPC: Instructions Per Cycle")
474 .precision(6);
475 ipc = committedInsts / numCycles;
476
477 totalIpc
478 .name(name() + ".ipc_total")
479 .desc("IPC: Total IPC of All Threads")
480 .precision(6);
481 totalIpc = sum(committedInsts) / numCycles;
482
483 this->fetch.regStats();
484 this->decode.regStats();
485 this->rename.regStats();
486 this->iew.regStats();
487 this->commit.regStats();
488 this->rob.regStats();
489
490 intRegfileReads
491 .name(name() + ".int_regfile_reads")
492 .desc("number of integer regfile reads")
493 .prereq(intRegfileReads);
494
495 intRegfileWrites
496 .name(name() + ".int_regfile_writes")
497 .desc("number of integer regfile writes")
498 .prereq(intRegfileWrites);
499
500 fpRegfileReads
501 .name(name() + ".fp_regfile_reads")
502 .desc("number of floating regfile reads")
503 .prereq(fpRegfileReads);
504
505 fpRegfileWrites
506 .name(name() + ".fp_regfile_writes")
507 .desc("number of floating regfile writes")
508 .prereq(fpRegfileWrites);
509
510 ccRegfileReads
511 .name(name() + ".cc_regfile_reads")
512 .desc("number of cc regfile reads")
513 .prereq(ccRegfileReads);
514
515 ccRegfileWrites
516 .name(name() + ".cc_regfile_writes")
517 .desc("number of cc regfile writes")
518 .prereq(ccRegfileWrites);
519
520 miscRegfileReads
521 .name(name() + ".misc_regfile_reads")
522 .desc("number of misc regfile reads")
523 .prereq(miscRegfileReads);
524
525 miscRegfileWrites
526 .name(name() + ".misc_regfile_writes")
527 .desc("number of misc regfile writes")
528 .prereq(miscRegfileWrites);
529}
530
531template <class Impl>
532void
533FullO3CPU<Impl>::tick()
534{
535 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
536 assert(!switchedOut());
537 assert(getDrainState() != Drainable::Drained);
538
539 ++numCycles;
540 ppCycles->notify(1);
541
542// activity = false;
543
544 //Tick each of the stages
545 fetch.tick();
546
547 decode.tick();
548
549 rename.tick();
550
551 iew.tick();
552
553 commit.tick();
554
555 // Now advance the time buffers
556 timeBuffer.advance();
557
558 fetchQueue.advance();
559 decodeQueue.advance();
560 renameQueue.advance();
561 iewQueue.advance();
562
563 activityRec.advance();
564
565 if (removeInstsThisCycle) {
566 cleanUpRemovedInsts();
567 }
568
569 if (!tickEvent.scheduled()) {
570 if (_status == SwitchedOut) {
571 DPRINTF(O3CPU, "Switched out!\n");
572 // increment stat
573 lastRunningCycle = curCycle();
574 } else if (!activityRec.active() || _status == Idle) {
575 DPRINTF(O3CPU, "Idle!\n");
576 lastRunningCycle = curCycle();
577 timesIdled++;
578 } else {
579 schedule(tickEvent, clockEdge(Cycles(1)));
580 DPRINTF(O3CPU, "Scheduling next tick!\n");
581 }
582 }
583
584 if (!FullSystem)
585 updateThreadPriority();
586
587 tryDrain();
588}
589
590template <class Impl>
591void
592FullO3CPU<Impl>::init()
593{
594 BaseCPU::init();
595
596 for (ThreadID tid = 0; tid < numThreads; ++tid) {
597 // Set noSquashFromTC so that the CPU doesn't squash when initially
598 // setting up registers.
599 thread[tid]->noSquashFromTC = true;
600 // Initialise the ThreadContext's memory proxies
601 thread[tid]->initMemProxies(thread[tid]->getTC());
602 }
603
604 if (FullSystem && !params()->switched_out) {
605 for (ThreadID tid = 0; tid < numThreads; tid++) {
606 ThreadContext *src_tc = threadContexts[tid];
607 TheISA::initCPU(src_tc, src_tc->contextId());
608 }
609 }
610
611 // Clear noSquashFromTC.
612 for (int tid = 0; tid < numThreads; ++tid)
613 thread[tid]->noSquashFromTC = false;
614
615 commit.setThreads(thread);
616}
617
618template <class Impl>
619void
620FullO3CPU<Impl>::startup()
621{
622 BaseCPU::startup();
623 for (int tid = 0; tid < numThreads; ++tid)
624 isa[tid]->startup(threadContexts[tid]);
625
626 fetch.startupStage();
627 decode.startupStage();
628 iew.startupStage();
629 rename.startupStage();
630 commit.startupStage();
631}
632
633template <class Impl>
634void
635FullO3CPU<Impl>::activateThread(ThreadID tid)
636{
637 list<ThreadID>::iterator isActive =
638 std::find(activeThreads.begin(), activeThreads.end(), tid);
639
640 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
641 assert(!switchedOut());
642
643 if (isActive == activeThreads.end()) {
644 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
645 tid);
646
647 activeThreads.push_back(tid);
648 }
649}
650
651template <class Impl>
652void
653FullO3CPU<Impl>::deactivateThread(ThreadID tid)
654{
655 //Remove From Active List, if Active
656 list<ThreadID>::iterator thread_it =
657 std::find(activeThreads.begin(), activeThreads.end(), tid);
658
659 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
660 assert(!switchedOut());
661
662 if (thread_it != activeThreads.end()) {
663 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
664 tid);
665 activeThreads.erase(thread_it);
666 }
667
668 fetch.deactivateThread(tid);
669 commit.deactivateThread(tid);
670}
671
672template <class Impl>
673Counter
674FullO3CPU<Impl>::totalInsts() const
675{
676 Counter total(0);
677
678 ThreadID size = thread.size();
679 for (ThreadID i = 0; i < size; i++)
680 total += thread[i]->numInst;
681
682 return total;
683}
684
685template <class Impl>
686Counter
687FullO3CPU<Impl>::totalOps() const
688{
689 Counter total(0);
690
691 ThreadID size = thread.size();
692 for (ThreadID i = 0; i < size; i++)
693 total += thread[i]->numOp;
694
695 return total;
696}
697
698template <class Impl>
699void
700FullO3CPU<Impl>::activateContext(ThreadID tid)
701{
702 assert(!switchedOut());
703
704 // Needs to set each stage to running as well.
705 activateThread(tid);
706
707 // We don't want to wake the CPU if it is drained. In that case,
708 // we just want to flag the thread as active and schedule the tick
709 // event from drainResume() instead.
710 if (getDrainState() == Drainable::Drained)
711 return;
712
713 // If we are time 0 or if the last activation time is in the past,
714 // schedule the next tick and wake up the fetch unit
715 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
716 scheduleTickEvent(Cycles(0));
717
718 // Be sure to signal that there's some activity so the CPU doesn't
719 // deschedule itself.
720 activityRec.activity();
721 fetch.wakeFromQuiesce();
722
723 Cycles cycles(curCycle() - lastRunningCycle);
724 // @todo: This is an oddity that is only here to match the stats
725 if (cycles != 0)
726 --cycles;
727 quiesceCycles += cycles;
728
729 lastActivatedCycle = curTick();
730
731 _status = Running;
732 }
733}
734
735template <class Impl>
736void
737FullO3CPU<Impl>::suspendContext(ThreadID tid)
738{
739 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
740 assert(!switchedOut());
741
742 deactivateThread(tid);
743
744 // If this was the last thread then unschedule the tick event.
745 if (activeThreads.size() == 0)
746 unscheduleTickEvent();
747
748 DPRINTF(Quiesce, "Suspending Context\n");
749 lastRunningCycle = curCycle();
750 _status = Idle;
751}
752
753template <class Impl>
754void
755FullO3CPU<Impl>::haltContext(ThreadID tid)
756{
757 //For now, this is the same as deallocate
758 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
759 assert(!switchedOut());
760
761 deactivateThread(tid);
762 removeThread(tid);
763}
764
765template <class Impl>
766void
767FullO3CPU<Impl>::insertThread(ThreadID tid)
768{
769 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
770 // Will change now that the PC and thread state is internal to the CPU
771 // and not in the ThreadContext.
772 ThreadContext *src_tc;
773 if (FullSystem)
774 src_tc = system->threadContexts[tid];
775 else
776 src_tc = tcBase(tid);
777
778 //Bind Int Regs to Rename Map
779 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
780 PhysRegIndex phys_reg = freeList.getIntReg();
781
782 renameMap[tid].setEntry(ireg,phys_reg);
783 scoreboard.setReg(phys_reg);
784 }
785
786 //Bind Float Regs to Rename Map
787 int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
788 for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
789 PhysRegIndex phys_reg = freeList.getFloatReg();
790
791 renameMap[tid].setEntry(freg,phys_reg);
792 scoreboard.setReg(phys_reg);
793 }
794
795 //Bind condition-code Regs to Rename Map
796 max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
797 for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
798 creg < max_reg; creg++) {
799 PhysRegIndex phys_reg = freeList.getCCReg();
800
801 renameMap[tid].setEntry(creg,phys_reg);
802 scoreboard.setReg(phys_reg);
803 }
804
805 //Copy Thread Data Into RegFile
806 //this->copyFromTC(tid);
807
808 //Set PC/NPC/NNPC
809 pcState(src_tc->pcState(), tid);
810
811 src_tc->setStatus(ThreadContext::Active);
812
813 activateContext(tid);
814
815 //Reset ROB/IQ/LSQ Entries
816 commit.rob->resetEntries();
817 iew.resetEntries();
818}
819
820template <class Impl>
821void
822FullO3CPU<Impl>::removeThread(ThreadID tid)
823{
824 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
825
826 // Copy Thread Data From RegFile
827 // If thread is suspended, it might be re-allocated
828 // this->copyToTC(tid);
829
830
831 // @todo: 2-27-2008: Fix how we free up rename mappings
832 // here to alleviate the case for double-freeing registers
833 // in SMT workloads.
834
835 // Unbind Int Regs from Rename Map
836 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
837 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
838
839 scoreboard.unsetReg(phys_reg);
840 freeList.addReg(phys_reg);
841 }
842
843 // Unbind Float Regs from Rename Map
844 int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
845 for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
846 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
847
848 scoreboard.unsetReg(phys_reg);
849 freeList.addReg(phys_reg);
850 }
851
852 // Unbind condition-code Regs from Rename Map
853 max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
854 for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
855 creg < max_reg; creg++) {
856 PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
857
858 scoreboard.unsetReg(phys_reg);
859 freeList.addReg(phys_reg);
860 }
861
862 // Squash Throughout Pipeline
863 DynInstPtr inst = commit.rob->readHeadInst(tid);
864 InstSeqNum squash_seq_num = inst->seqNum;
865 fetch.squash(0, squash_seq_num, inst, tid);
866 decode.squash(tid);
867 rename.squash(squash_seq_num, tid);
868 iew.squash(tid);
869 iew.ldstQueue.squash(squash_seq_num, tid);
870 commit.rob->squash(squash_seq_num, tid);
871
872
873 assert(iew.instQueue.getCount(tid) == 0);
874 assert(iew.ldstQueue.getCount(tid) == 0);
875
876 // Reset ROB/IQ/LSQ Entries
877
878 // Commented out for now. This should be possible to do by
879 // telling all the pipeline stages to drain first, and then
880 // checking until the drain completes. Once the pipeline is
881 // drained, call resetEntries(). - 10-09-06 ktlim
882/*
883 if (activeThreads.size() >= 1) {
884 commit.rob->resetEntries();
885 iew.resetEntries();
886 }
887*/
888}
889
890template <class Impl>
891Fault
892FullO3CPU<Impl>::hwrei(ThreadID tid)
893{
894#if THE_ISA == ALPHA_ISA
895 // Need to clear the lock flag upon returning from an interrupt.
896 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
897
898 this->thread[tid]->kernelStats->hwrei();
899
900 // FIXME: XXX check for interrupts? XXX
901#endif
902 return NoFault;
903}
904
905template <class Impl>
906bool
907FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
908{
909#if THE_ISA == ALPHA_ISA
910 if (this->thread[tid]->kernelStats)
911 this->thread[tid]->kernelStats->callpal(palFunc,
912 this->threadContexts[tid]);
913
914 switch (palFunc) {
915 case PAL::halt:
916 halt();
917 if (--System::numSystemsRunning == 0)
918 exitSimLoop("all cpus halted");
919 break;
920
921 case PAL::bpt:
922 case PAL::bugchk:
923 if (this->system->breakpoint())
924 return false;
925 break;
926 }
927#endif
928 return true;
929}
930
931template <class Impl>
932Fault
933FullO3CPU<Impl>::getInterrupts()
934{
935 // Check if there are any outstanding interrupts
936 return this->interrupts->getInterrupt(this->threadContexts[0]);
937}
938
939template <class Impl>
940void
941FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
942{
943 // Check for interrupts here. For now can copy the code that
944 // exists within isa_fullsys_traits.hh. Also assume that thread 0
945 // is the one that handles the interrupts.
946 // @todo: Possibly consolidate the interrupt checking code.
947 // @todo: Allow other threads to handle interrupts.
948
949 assert(interrupt != NoFault);
950 this->interrupts->updateIntrInfo(this->threadContexts[0]);
951
952 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
953 this->trap(interrupt, 0, nullptr);
954}
955
956template <class Impl>
957void
958FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
959 const StaticInstPtr &inst)
960{
961 // Pass the thread's TC into the invoke method.
962 fault->invoke(this->threadContexts[tid], inst);
963}
964
965template <class Impl>
966void
967FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
968{
969 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
970
971 DPRINTF(Activity,"Activity: syscall() called.\n");
972
973 // Temporarily increase this by one to account for the syscall
974 // instruction.
975 ++(this->thread[tid]->funcExeInst);
976
977 // Execute the actual syscall.
978 this->thread[tid]->syscall(callnum);
979
980 // Decrease funcExeInst by one as the normal commit will handle
981 // incrementing it.
982 --(this->thread[tid]->funcExeInst);
983}
984
985template <class Impl>
986void
987FullO3CPU<Impl>::serializeThread(std::ostream &os, ThreadID tid)
988{
989 thread[tid]->serialize(os);
990}
991
992template <class Impl>
993void
994FullO3CPU<Impl>::unserializeThread(Checkpoint *cp, const std::string §ion,
995 ThreadID tid)
996{
997 thread[tid]->unserialize(cp, section);
998}
999
1000template <class Impl>
1001unsigned int
1002FullO3CPU<Impl>::drain(DrainManager *drain_manager)
1003{
1004 // If the CPU isn't doing anything, then return immediately.
1005 if (switchedOut()) {
1006 setDrainState(Drainable::Drained);
1007 return 0;
1008 }
1009
1010 DPRINTF(Drain, "Draining...\n");
1011 setDrainState(Drainable::Draining);
1012
1013 // We only need to signal a drain to the commit stage as this
1014 // initiates squashing controls the draining. Once the commit
1015 // stage commits an instruction where it is safe to stop, it'll
1016 // squash the rest of the instructions in the pipeline and force
1017 // the fetch stage to stall. The pipeline will be drained once all
1018 // in-flight instructions have retired.
1019 commit.drain();
1020
1021 // Wake the CPU and record activity so everything can drain out if
1022 // the CPU was not able to immediately drain.
1023 if (!isDrained()) {
1024 drainManager = drain_manager;
1025
1026 wakeCPU();
1027 activityRec.activity();
1028
1029 DPRINTF(Drain, "CPU not drained\n");
1030
1031 return 1;
1032 } else {
1033 setDrainState(Drainable::Drained);
1034 DPRINTF(Drain, "CPU is already drained\n");
1035 if (tickEvent.scheduled())
1036 deschedule(tickEvent);
1037
1038 // Flush out any old data from the time buffers. In
1039 // particular, there might be some data in flight from the
1040 // fetch stage that isn't visible in any of the CPU buffers we
1041 // test in isDrained().
1042 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1043 timeBuffer.advance();
1044 fetchQueue.advance();
1045 decodeQueue.advance();
1046 renameQueue.advance();
1047 iewQueue.advance();
1048 }
1049
1050 drainSanityCheck();
1051 return 0;
1052 }
1053}
1054
1055template <class Impl>
1056bool
1057FullO3CPU<Impl>::tryDrain()
1058{
1059 if (!drainManager || !isDrained())
1060 return false;
1061
1062 if (tickEvent.scheduled())
1063 deschedule(tickEvent);
1064
1065 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1066 drainManager->signalDrainDone();
1067 drainManager = NULL;
1068
1069 return true;
1070}
1071
1072template <class Impl>
1073void
1074FullO3CPU<Impl>::drainSanityCheck() const
1075{
1076 assert(isDrained());
1077 fetch.drainSanityCheck();
1078 decode.drainSanityCheck();
1079 rename.drainSanityCheck();
1080 iew.drainSanityCheck();
1081 commit.drainSanityCheck();
1082}
1083
1084template <class Impl>
1085bool
1086FullO3CPU<Impl>::isDrained() const
1087{
1088 bool drained(true);
1089
1090 if (!instList.empty() || !removeList.empty()) {
1091 DPRINTF(Drain, "Main CPU structures not drained.\n");
1092 drained = false;
1093 }
1094
1095 if (!fetch.isDrained()) {
1096 DPRINTF(Drain, "Fetch not drained.\n");
1097 drained = false;
1098 }
1099
1100 if (!decode.isDrained()) {
1101 DPRINTF(Drain, "Decode not drained.\n");
1102 drained = false;
1103 }
1104
1105 if (!rename.isDrained()) {
1106 DPRINTF(Drain, "Rename not drained.\n");
1107 drained = false;
1108 }
1109
1110 if (!iew.isDrained()) {
1111 DPRINTF(Drain, "IEW not drained.\n");
1112 drained = false;
1113 }
1114
1115 if (!commit.isDrained()) {
1116 DPRINTF(Drain, "Commit not drained.\n");
1117 drained = false;
1118 }
1119
1120 return drained;
1121}
1122
1123template <class Impl>
1124void
1125FullO3CPU<Impl>::commitDrained(ThreadID tid)
1126{
1127 fetch.drainStall(tid);
1128}
1129
1130template <class Impl>
1131void
1132FullO3CPU<Impl>::drainResume()
1133{
1134 setDrainState(Drainable::Running);
1135 if (switchedOut())
1136 return;
1137
1138 DPRINTF(Drain, "Resuming...\n");
1139 verifyMemoryMode();
1140
1141 fetch.drainResume();
1142 commit.drainResume();
1143
1144 _status = Idle;
1145 for (ThreadID i = 0; i < thread.size(); i++) {
1146 if (thread[i]->status() == ThreadContext::Active) {
1147 DPRINTF(Drain, "Activating thread: %i\n", i);
1148 activateThread(i);
1149 _status = Running;
1150 }
1151 }
1152
1153 assert(!tickEvent.scheduled());
1154 if (_status == Running)
1155 schedule(tickEvent, nextCycle());
1156}
1157
1158template <class Impl>
1159void
1160FullO3CPU<Impl>::switchOut()
1161{
1162 DPRINTF(O3CPU, "Switching out\n");
1163 BaseCPU::switchOut();
1164
1165 activityRec.reset();
1166
1167 _status = SwitchedOut;
1168
1169 if (checker)
1170 checker->switchOut();
1171}
1172
1173template <class Impl>
1174void
1175FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1176{
1177 BaseCPU::takeOverFrom(oldCPU);
1178
1179 fetch.takeOverFrom();
1180 decode.takeOverFrom();
1181 rename.takeOverFrom();
1182 iew.takeOverFrom();
1183 commit.takeOverFrom();
1184
1185 assert(!tickEvent.scheduled());
1186
1187 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1188 if (oldO3CPU)
1189 globalSeqNum = oldO3CPU->globalSeqNum;
1190
1191 lastRunningCycle = curCycle();
1192 _status = Idle;
1193}
1194
1195template <class Impl>
1196void
1197FullO3CPU<Impl>::verifyMemoryMode() const
1198{
1199 if (!system->isTimingMode()) {
1200 fatal("The O3 CPU requires the memory system to be in "
1201 "'timing' mode.\n");
1202 }
1203}
1204
1205template <class Impl>
1206TheISA::MiscReg
1207FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1208{
1209 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1210}
1211
1212template <class Impl>
1213TheISA::MiscReg
1214FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1215{
1216 miscRegfileReads++;
1217 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1218}
1219
1220template <class Impl>
1221void
1222FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1223 const TheISA::MiscReg &val, ThreadID tid)
1224{
1225 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1226}
1227
1228template <class Impl>
1229void
1230FullO3CPU<Impl>::setMiscReg(int misc_reg,
1231 const TheISA::MiscReg &val, ThreadID tid)
1232{
1233 miscRegfileWrites++;
1234 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1235}
1236
1237template <class Impl>
1238uint64_t
1239FullO3CPU<Impl>::readIntReg(int reg_idx)
1240{
1241 intRegfileReads++;
1242 return regFile.readIntReg(reg_idx);
1243}
1244
1245template <class Impl>
1246FloatReg
1247FullO3CPU<Impl>::readFloatReg(int reg_idx)
1248{
1249 fpRegfileReads++;
1250 return regFile.readFloatReg(reg_idx);
1251}
1252
1253template <class Impl>
1254FloatRegBits
1255FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1256{
1257 fpRegfileReads++;
1258 return regFile.readFloatRegBits(reg_idx);
1259}
1260
1261template <class Impl>
1262CCReg
1263FullO3CPU<Impl>::readCCReg(int reg_idx)
1264{
1265 ccRegfileReads++;
1266 return regFile.readCCReg(reg_idx);
1267}
1268
1269template <class Impl>
1270void
1271FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1272{
1273 intRegfileWrites++;
1274 regFile.setIntReg(reg_idx, val);
1275}
1276
1277template <class Impl>
1278void
1279FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1280{
1281 fpRegfileWrites++;
1282 regFile.setFloatReg(reg_idx, val);
1283}
1284
1285template <class Impl>
1286void
1287FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1288{
1289 fpRegfileWrites++;
1290 regFile.setFloatRegBits(reg_idx, val);
1291}
1292
1293template <class Impl>
1294void
1295FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
1296{
1297 ccRegfileWrites++;
1298 regFile.setCCReg(reg_idx, val);
1299}
1300
1301template <class Impl>
1302uint64_t
1303FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1304{
1305 intRegfileReads++;
1306 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1307
1308 return regFile.readIntReg(phys_reg);
1309}
1310
1311template <class Impl>
1312float
1313FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1314{
1315 fpRegfileReads++;
1316 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1317
1318 return regFile.readFloatReg(phys_reg);
1319}
1320
1321template <class Impl>
1322uint64_t
1323FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1324{
1325 fpRegfileReads++;
1326 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1327
1328 return regFile.readFloatRegBits(phys_reg);
1329}
1330
1331template <class Impl>
1332CCReg
1333FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1334{
1335 ccRegfileReads++;
1336 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1337
1338 return regFile.readCCReg(phys_reg);
1339}
1340
1341template <class Impl>
1342void
1343FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1344{
1345 intRegfileWrites++;
1346 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1347
1348 regFile.setIntReg(phys_reg, val);
1349}
1350
1351template <class Impl>
1352void
1353FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1354{
1355 fpRegfileWrites++;
1356 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1357
1358 regFile.setFloatReg(phys_reg, val);
1359}
1360
1361template <class Impl>
1362void
1363FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1364{
1365 fpRegfileWrites++;
1366 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1367
1368 regFile.setFloatRegBits(phys_reg, val);
1369}
1370
1371template <class Impl>
1372void
1373FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1374{
1375 ccRegfileWrites++;
1376 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1377
1378 regFile.setCCReg(phys_reg, val);
1379}
1380
1381template <class Impl>
1382TheISA::PCState
1383FullO3CPU<Impl>::pcState(ThreadID tid)
1384{
1385 return commit.pcState(tid);
1386}
1387
1388template <class Impl>
1389void
1390FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1391{
1392 commit.pcState(val, tid);
1393}
1394
1395template <class Impl>
1396Addr
1397FullO3CPU<Impl>::instAddr(ThreadID tid)
1398{
1399 return commit.instAddr(tid);
1400}
1401
1402template <class Impl>
1403Addr
1404FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1405{
1406 return commit.nextInstAddr(tid);
1407}
1408
1409template <class Impl>
1410MicroPC
1411FullO3CPU<Impl>::microPC(ThreadID tid)
1412{
1413 return commit.microPC(tid);
1414}
1415
1416template <class Impl>
1417void
1418FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1419{
1420 this->thread[tid]->noSquashFromTC = true;
1421 this->commit.generateTCEvent(tid);
1422}
1423
1424template <class Impl>
1425typename FullO3CPU<Impl>::ListIt
1426FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1427{
1428 instList.push_back(inst);
1429
1430 return --(instList.end());
1431}
1432
1433template <class Impl>
1434void
1435FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1436{
1437 // Keep an instruction count.
1438 if (!inst->isMicroop() || inst->isLastMicroop()) {
1439 thread[tid]->numInst++;
1440 thread[tid]->numInsts++;
1441 committedInsts[tid]++;
1442 }
1443 thread[tid]->numOp++;
1444 thread[tid]->numOps++;
1445 committedOps[tid]++;
1446
1447 system->totalNumInsts++;
1448 // Check for instruction-count-based events.
1449 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1450 system->instEventQueue.serviceEvents(system->totalNumInsts);
1451
1452 probeInstCommit(inst->staticInst);
1453}
1454
1455template <class Impl>
1456void
1457FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1458{
1459 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1460 "[sn:%lli]\n",
1461 inst->threadNumber, inst->pcState(), inst->seqNum);
1462
1463 removeInstsThisCycle = true;
1464
1465 // Remove the front instruction.
1466 removeList.push(inst->getInstListIt());
1467}
1468
1469template <class Impl>
1470void
1471FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1472{
1473 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1474 " list.\n", tid);
1475
1476 ListIt end_it;
1477
1478 bool rob_empty = false;
1479
1480 if (instList.empty()) {
1481 return;
1482 } else if (rob.isEmpty(tid)) {
1483 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1484 end_it = instList.begin();
1485 rob_empty = true;
1486 } else {
1487 end_it = (rob.readTailInst(tid))->getInstListIt();
1488 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1489 }
1490
1491 removeInstsThisCycle = true;
1492
1493 ListIt inst_it = instList.end();
1494
1495 inst_it--;
1496
1497 // Walk through the instruction list, removing any instructions
1498 // that were inserted after the given instruction iterator, end_it.
1499 while (inst_it != end_it) {
1500 assert(!instList.empty());
1501
1502 squashInstIt(inst_it, tid);
1503
1504 inst_it--;
1505 }
1506
1507 // If the ROB was empty, then we actually need to remove the first
1508 // instruction as well.
1509 if (rob_empty) {
1510 squashInstIt(inst_it, tid);
1511 }
1512}
1513
1514template <class Impl>
1515void
1516FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1517{
1518 assert(!instList.empty());
1519
1520 removeInstsThisCycle = true;
1521
1522 ListIt inst_iter = instList.end();
1523
1524 inst_iter--;
1525
1526 DPRINTF(O3CPU, "Deleting instructions from instruction "
1527 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1528 tid, seq_num, (*inst_iter)->seqNum);
1529
1530 while ((*inst_iter)->seqNum > seq_num) {
1531
1532 bool break_loop = (inst_iter == instList.begin());
1533
1534 squashInstIt(inst_iter, tid);
1535
1536 inst_iter--;
1537
1538 if (break_loop)
1539 break;
1540 }
1541}
1542
1543template <class Impl>
1544inline void
1545FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1546{
1547 if ((*instIt)->threadNumber == tid) {
1548 DPRINTF(O3CPU, "Squashing instruction, "
1549 "[tid:%i] [sn:%lli] PC %s\n",
1550 (*instIt)->threadNumber,
1551 (*instIt)->seqNum,
1552 (*instIt)->pcState());
1553
1554 // Mark it as squashed.
1555 (*instIt)->setSquashed();
1556
1557 // @todo: Formulate a consistent method for deleting
1558 // instructions from the instruction list
1559 // Remove the instruction from the list.
1560 removeList.push(instIt);
1561 }
1562}
1563
1564template <class Impl>
1565void
1566FullO3CPU<Impl>::cleanUpRemovedInsts()
1567{
1568 while (!removeList.empty()) {
1569 DPRINTF(O3CPU, "Removing instruction, "
1570 "[tid:%i] [sn:%lli] PC %s\n",
1571 (*removeList.front())->threadNumber,
1572 (*removeList.front())->seqNum,
1573 (*removeList.front())->pcState());
1574
1575 instList.erase(removeList.front());
1576
1577 removeList.pop();
1578 }
1579
1580 removeInstsThisCycle = false;
1581}
1582/*
1583template <class Impl>
1584void
1585FullO3CPU<Impl>::removeAllInsts()
1586{
1587 instList.clear();
1588}
1589*/
1590template <class Impl>
1591void
1592FullO3CPU<Impl>::dumpInsts()
1593{
1594 int num = 0;
1595
1596 ListIt inst_list_it = instList.begin();
1597
1598 cprintf("Dumping Instruction List\n");
1599
1600 while (inst_list_it != instList.end()) {
1601 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1602 "Squashed:%i\n\n",
1603 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1604 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1605 (*inst_list_it)->isSquashed());
1606 inst_list_it++;
1607 ++num;
1608 }
1609}
1610/*
1611template <class Impl>
1612void
1613FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1614{
1615 iew.wakeDependents(inst);
1616}
1617*/
1618template <class Impl>
1619void
1620FullO3CPU<Impl>::wakeCPU()
1621{
1622 if (activityRec.active() || tickEvent.scheduled()) {
1623 DPRINTF(Activity, "CPU already running.\n");
1624 return;
1625 }
1626
1627 DPRINTF(Activity, "Waking up CPU\n");
1628
1629 Cycles cycles(curCycle() - lastRunningCycle);
1630 // @todo: This is an oddity that is only here to match the stats
1631 if (cycles > 1) {
1632 --cycles;
1633 idleCycles += cycles;
1634 numCycles += cycles;
1635 ppCycles->notify(cycles);
1636 }
1637
1638 schedule(tickEvent, clockEdge());
1639}
1640
1641template <class Impl>
1642void
1643FullO3CPU<Impl>::wakeup()
1644{
1645 if (this->thread[0]->status() != ThreadContext::Suspended)
1646 return;
1647
1648 this->wakeCPU();
1649
1650 DPRINTF(Quiesce, "Suspended Processor woken\n");
1651 this->threadContexts[0]->activate();
1652}
1653
1654template <class Impl>
1655ThreadID
1656FullO3CPU<Impl>::getFreeTid()
1657{
1658 for (ThreadID tid = 0; tid < numThreads; tid++) {
1659 if (!tids[tid]) {
1660 tids[tid] = true;
1661 return tid;
1662 }
1663 }
1664
1665 return InvalidThreadID;
1666}
1667
1668template <class Impl>
1669void
1670FullO3CPU<Impl>::updateThreadPriority()
1671{
1672 if (activeThreads.size() > 1) {
1673 //DEFAULT TO ROUND ROBIN SCHEME
1674 //e.g. Move highest priority to end of thread list
1675 list<ThreadID>::iterator list_begin = activeThreads.begin();
1676
1677 unsigned high_thread = *list_begin;
1678
1679 activeThreads.erase(list_begin);
1680
1681 activeThreads.push_back(high_thread);
1682 }
1683}
1684
1685// Forward declaration of FullO3CPU.
1686template class FullO3CPU<O3CPUImpl>;
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#include "arch/kernel_stats.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/checker/thread_context.hh"
51#include "cpu/o3/cpu.hh"
52#include "cpu/o3/isa_specific.hh"
53#include "cpu/o3/thread_context.hh"
54#include "cpu/activity.hh"
55#include "cpu/quiesce_event.hh"
56#include "cpu/simple_thread.hh"
57#include "cpu/thread_context.hh"
58#include "debug/Activity.hh"
59#include "debug/Drain.hh"
60#include "debug/O3CPU.hh"
61#include "debug/Quiesce.hh"
62#include "enums/MemoryMode.hh"
63#include "sim/core.hh"
64#include "sim/full_system.hh"
65#include "sim/process.hh"
66#include "sim/stat_control.hh"
67#include "sim/system.hh"
68
69#if THE_ISA == ALPHA_ISA
70#include "arch/alpha/osfpal.hh"
71#include "debug/Activity.hh"
72#endif
73
74struct BaseCPUParams;
75
76using namespace TheISA;
77using namespace std;
78
79BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
80 : BaseCPU(params)
81{
82}
83
84void
85BaseO3CPU::regStats()
86{
87 BaseCPU::regStats();
88}
89
90template<class Impl>
91bool
92FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
93{
94 DPRINTF(O3CPU, "Fetch unit received timing\n");
95 // We shouldn't ever get a block in ownership state
96 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
97 fetch->processCacheCompletion(pkt);
98
99 return true;
100}
101
102template<class Impl>
103void
104FullO3CPU<Impl>::IcachePort::recvRetry()
105{
106 fetch->recvRetry();
107}
108
109template <class Impl>
110bool
111FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
112{
113 return lsq->recvTimingResp(pkt);
114}
115
116template <class Impl>
117void
118FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
119{
120 lsq->recvTimingSnoopReq(pkt);
121}
122
123template <class Impl>
124void
125FullO3CPU<Impl>::DcachePort::recvRetry()
126{
127 lsq->recvRetry();
128}
129
130template <class Impl>
131FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
132 : Event(CPU_Tick_Pri), cpu(c)
133{
134}
135
136template <class Impl>
137void
138FullO3CPU<Impl>::TickEvent::process()
139{
140 cpu->tick();
141}
142
143template <class Impl>
144const char *
145FullO3CPU<Impl>::TickEvent::description() const
146{
147 return "FullO3CPU tick";
148}
149
150template <class Impl>
151FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
152 : BaseO3CPU(params),
153 itb(params->itb),
154 dtb(params->dtb),
155 tickEvent(this),
156#ifndef NDEBUG
157 instcount(0),
158#endif
159 removeInstsThisCycle(false),
160 fetch(this, params),
161 decode(this, params),
162 rename(this, params),
163 iew(this, params),
164 commit(this, params),
165
166 regFile(params->numPhysIntRegs,
167 params->numPhysFloatRegs,
168 params->numPhysCCRegs),
169
170 freeList(name() + ".freelist", ®File),
171
172 rob(this, params),
173
174 scoreboard(name() + ".scoreboard",
175 regFile.totalNumPhysRegs(), TheISA::NumMiscRegs,
176 TheISA::ZeroReg, TheISA::ZeroReg),
177
178 isa(numThreads, NULL),
179
180 icachePort(&fetch, this),
181 dcachePort(&iew.ldstQueue, this),
182
183 timeBuffer(params->backComSize, params->forwardComSize),
184 fetchQueue(params->backComSize, params->forwardComSize),
185 decodeQueue(params->backComSize, params->forwardComSize),
186 renameQueue(params->backComSize, params->forwardComSize),
187 iewQueue(params->backComSize, params->forwardComSize),
188 activityRec(name(), NumStages,
189 params->backComSize + params->forwardComSize,
190 params->activity),
191
192 globalSeqNum(1),
193 system(params->system),
194 drainManager(NULL),
195 lastRunningCycle(curCycle())
196{
197 if (!params->switched_out) {
198 _status = Running;
199 } else {
200 _status = SwitchedOut;
201 }
202
203 if (params->checker) {
204 BaseCPU *temp_checker = params->checker;
205 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
206 checker->setIcachePort(&icachePort);
207 checker->setSystem(params->system);
208 } else {
209 checker = NULL;
210 }
211
212 if (!FullSystem) {
213 thread.resize(numThreads);
214 tids.resize(numThreads);
215 }
216
217 // The stages also need their CPU pointer setup. However this
218 // must be done at the upper level CPU because they have pointers
219 // to the upper level CPU, and not this FullO3CPU.
220
221 // Set up Pointers to the activeThreads list for each stage
222 fetch.setActiveThreads(&activeThreads);
223 decode.setActiveThreads(&activeThreads);
224 rename.setActiveThreads(&activeThreads);
225 iew.setActiveThreads(&activeThreads);
226 commit.setActiveThreads(&activeThreads);
227
228 // Give each of the stages the time buffer they will use.
229 fetch.setTimeBuffer(&timeBuffer);
230 decode.setTimeBuffer(&timeBuffer);
231 rename.setTimeBuffer(&timeBuffer);
232 iew.setTimeBuffer(&timeBuffer);
233 commit.setTimeBuffer(&timeBuffer);
234
235 // Also setup each of the stages' queues.
236 fetch.setFetchQueue(&fetchQueue);
237 decode.setFetchQueue(&fetchQueue);
238 commit.setFetchQueue(&fetchQueue);
239 decode.setDecodeQueue(&decodeQueue);
240 rename.setDecodeQueue(&decodeQueue);
241 rename.setRenameQueue(&renameQueue);
242 iew.setRenameQueue(&renameQueue);
243 iew.setIEWQueue(&iewQueue);
244 commit.setIEWQueue(&iewQueue);
245 commit.setRenameQueue(&renameQueue);
246
247 commit.setIEWStage(&iew);
248 rename.setIEWStage(&iew);
249 rename.setCommitStage(&commit);
250
251 ThreadID active_threads;
252 if (FullSystem) {
253 active_threads = 1;
254 } else {
255 active_threads = params->workload.size();
256
257 if (active_threads > Impl::MaxThreads) {
258 panic("Workload Size too large. Increase the 'MaxThreads' "
259 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
260 "or edit your workload size.");
261 }
262 }
263
264 //Make Sure That this a Valid Architeture
265 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
266 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
267 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
268
269 rename.setScoreboard(&scoreboard);
270 iew.setScoreboard(&scoreboard);
271
272 // Setup the rename map for whichever stages need it.
273 for (ThreadID tid = 0; tid < numThreads; tid++) {
274 isa[tid] = params->isa[tid];
275
276 // Only Alpha has an FP zero register, so for other ISAs we
277 // use an invalid FP register index to avoid special treatment
278 // of any valid FP reg.
279 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
280 RegIndex fpZeroReg =
281 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
282
283 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
284 &freeList);
285
286 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
287 &freeList);
288 }
289
290 // Initialize rename map to assign physical registers to the
291 // architectural registers for active threads only.
292 for (ThreadID tid = 0; tid < active_threads; tid++) {
293 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
294 // Note that we can't use the rename() method because we don't
295 // want special treatment for the zero register at this point
296 PhysRegIndex phys_reg = freeList.getIntReg();
297 renameMap[tid].setIntEntry(ridx, phys_reg);
298 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
299 }
300
301 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
302 PhysRegIndex phys_reg = freeList.getFloatReg();
303 renameMap[tid].setFloatEntry(ridx, phys_reg);
304 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
305 }
306
307 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
308 PhysRegIndex phys_reg = freeList.getCCReg();
309 renameMap[tid].setCCEntry(ridx, phys_reg);
310 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
311 }
312 }
313
314 rename.setRenameMap(renameMap);
315 commit.setRenameMap(commitRenameMap);
316 rename.setFreeList(&freeList);
317
318 // Setup the ROB for whichever stages need it.
319 commit.setROB(&rob);
320
321 lastActivatedCycle = 0;
322#if 0
323 // Give renameMap & rename stage access to the freeList;
324 for (ThreadID tid = 0; tid < numThreads; tid++)
325 globalSeqNum[tid] = 1;
326#endif
327
328 DPRINTF(O3CPU, "Creating O3CPU object.\n");
329
330 // Setup any thread state.
331 this->thread.resize(this->numThreads);
332
333 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
334 if (FullSystem) {
335 // SMT is not supported in FS mode yet.
336 assert(this->numThreads == 1);
337 this->thread[tid] = new Thread(this, 0, NULL);
338 } else {
339 if (tid < params->workload.size()) {
340 DPRINTF(O3CPU, "Workload[%i] process is %#x",
341 tid, this->thread[tid]);
342 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
343 (typename Impl::O3CPU *)(this),
344 tid, params->workload[tid]);
345
346 //usedTids[tid] = true;
347 //threadMap[tid] = tid;
348 } else {
349 //Allocate Empty thread so M5 can use later
350 //when scheduling threads to CPU
351 Process* dummy_proc = NULL;
352
353 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
354 (typename Impl::O3CPU *)(this),
355 tid, dummy_proc);
356 //usedTids[tid] = false;
357 }
358 }
359
360 ThreadContext *tc;
361
362 // Setup the TC that will serve as the interface to the threads/CPU.
363 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
364
365 tc = o3_tc;
366
367 // If we're using a checker, then the TC should be the
368 // CheckerThreadContext.
369 if (params->checker) {
370 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
371 o3_tc, this->checker);
372 }
373
374 o3_tc->cpu = (typename Impl::O3CPU *)(this);
375 assert(o3_tc->cpu);
376 o3_tc->thread = this->thread[tid];
377
378 if (FullSystem) {
379 // Setup quiesce event.
380 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
381 }
382 // Give the thread the TC.
383 this->thread[tid]->tc = tc;
384
385 // Add the TC to the CPU's list of TC's.
386 this->threadContexts.push_back(tc);
387 }
388
389 // FullO3CPU always requires an interrupt controller.
390 if (!params->switched_out && !interrupts) {
391 fatal("FullO3CPU %s has no interrupt controller.\n"
392 "Ensure createInterruptController() is called.\n", name());
393 }
394
395 for (ThreadID tid = 0; tid < this->numThreads; tid++)
396 this->thread[tid]->setFuncExeInst(0);
397}
398
399template <class Impl>
400FullO3CPU<Impl>::~FullO3CPU()
401{
402}
403
404template <class Impl>
405void
406FullO3CPU<Impl>::regProbePoints()
407{
408 BaseCPU::regProbePoints();
409
410 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
411 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
412
413 fetch.regProbePoints();
414 iew.regProbePoints();
415 commit.regProbePoints();
416}
417
418template <class Impl>
419void
420FullO3CPU<Impl>::regStats()
421{
422 BaseO3CPU::regStats();
423
424 // Register any of the O3CPU's stats here.
425 timesIdled
426 .name(name() + ".timesIdled")
427 .desc("Number of times that the entire CPU went into an idle state and"
428 " unscheduled itself")
429 .prereq(timesIdled);
430
431 idleCycles
432 .name(name() + ".idleCycles")
433 .desc("Total number of cycles that the CPU has spent unscheduled due "
434 "to idling")
435 .prereq(idleCycles);
436
437 quiesceCycles
438 .name(name() + ".quiesceCycles")
439 .desc("Total number of cycles that CPU has spent quiesced or waiting "
440 "for an interrupt")
441 .prereq(quiesceCycles);
442
443 // Number of Instructions simulated
444 // --------------------------------
445 // Should probably be in Base CPU but need templated
446 // MaxThreads so put in here instead
447 committedInsts
448 .init(numThreads)
449 .name(name() + ".committedInsts")
450 .desc("Number of Instructions Simulated")
451 .flags(Stats::total);
452
453 committedOps
454 .init(numThreads)
455 .name(name() + ".committedOps")
456 .desc("Number of Ops (including micro ops) Simulated")
457 .flags(Stats::total);
458
459 cpi
460 .name(name() + ".cpi")
461 .desc("CPI: Cycles Per Instruction")
462 .precision(6);
463 cpi = numCycles / committedInsts;
464
465 totalCpi
466 .name(name() + ".cpi_total")
467 .desc("CPI: Total CPI of All Threads")
468 .precision(6);
469 totalCpi = numCycles / sum(committedInsts);
470
471 ipc
472 .name(name() + ".ipc")
473 .desc("IPC: Instructions Per Cycle")
474 .precision(6);
475 ipc = committedInsts / numCycles;
476
477 totalIpc
478 .name(name() + ".ipc_total")
479 .desc("IPC: Total IPC of All Threads")
480 .precision(6);
481 totalIpc = sum(committedInsts) / numCycles;
482
483 this->fetch.regStats();
484 this->decode.regStats();
485 this->rename.regStats();
486 this->iew.regStats();
487 this->commit.regStats();
488 this->rob.regStats();
489
490 intRegfileReads
491 .name(name() + ".int_regfile_reads")
492 .desc("number of integer regfile reads")
493 .prereq(intRegfileReads);
494
495 intRegfileWrites
496 .name(name() + ".int_regfile_writes")
497 .desc("number of integer regfile writes")
498 .prereq(intRegfileWrites);
499
500 fpRegfileReads
501 .name(name() + ".fp_regfile_reads")
502 .desc("number of floating regfile reads")
503 .prereq(fpRegfileReads);
504
505 fpRegfileWrites
506 .name(name() + ".fp_regfile_writes")
507 .desc("number of floating regfile writes")
508 .prereq(fpRegfileWrites);
509
510 ccRegfileReads
511 .name(name() + ".cc_regfile_reads")
512 .desc("number of cc regfile reads")
513 .prereq(ccRegfileReads);
514
515 ccRegfileWrites
516 .name(name() + ".cc_regfile_writes")
517 .desc("number of cc regfile writes")
518 .prereq(ccRegfileWrites);
519
520 miscRegfileReads
521 .name(name() + ".misc_regfile_reads")
522 .desc("number of misc regfile reads")
523 .prereq(miscRegfileReads);
524
525 miscRegfileWrites
526 .name(name() + ".misc_regfile_writes")
527 .desc("number of misc regfile writes")
528 .prereq(miscRegfileWrites);
529}
530
531template <class Impl>
532void
533FullO3CPU<Impl>::tick()
534{
535 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
536 assert(!switchedOut());
537 assert(getDrainState() != Drainable::Drained);
538
539 ++numCycles;
540 ppCycles->notify(1);
541
542// activity = false;
543
544 //Tick each of the stages
545 fetch.tick();
546
547 decode.tick();
548
549 rename.tick();
550
551 iew.tick();
552
553 commit.tick();
554
555 // Now advance the time buffers
556 timeBuffer.advance();
557
558 fetchQueue.advance();
559 decodeQueue.advance();
560 renameQueue.advance();
561 iewQueue.advance();
562
563 activityRec.advance();
564
565 if (removeInstsThisCycle) {
566 cleanUpRemovedInsts();
567 }
568
569 if (!tickEvent.scheduled()) {
570 if (_status == SwitchedOut) {
571 DPRINTF(O3CPU, "Switched out!\n");
572 // increment stat
573 lastRunningCycle = curCycle();
574 } else if (!activityRec.active() || _status == Idle) {
575 DPRINTF(O3CPU, "Idle!\n");
576 lastRunningCycle = curCycle();
577 timesIdled++;
578 } else {
579 schedule(tickEvent, clockEdge(Cycles(1)));
580 DPRINTF(O3CPU, "Scheduling next tick!\n");
581 }
582 }
583
584 if (!FullSystem)
585 updateThreadPriority();
586
587 tryDrain();
588}
589
590template <class Impl>
591void
592FullO3CPU<Impl>::init()
593{
594 BaseCPU::init();
595
596 for (ThreadID tid = 0; tid < numThreads; ++tid) {
597 // Set noSquashFromTC so that the CPU doesn't squash when initially
598 // setting up registers.
599 thread[tid]->noSquashFromTC = true;
600 // Initialise the ThreadContext's memory proxies
601 thread[tid]->initMemProxies(thread[tid]->getTC());
602 }
603
604 if (FullSystem && !params()->switched_out) {
605 for (ThreadID tid = 0; tid < numThreads; tid++) {
606 ThreadContext *src_tc = threadContexts[tid];
607 TheISA::initCPU(src_tc, src_tc->contextId());
608 }
609 }
610
611 // Clear noSquashFromTC.
612 for (int tid = 0; tid < numThreads; ++tid)
613 thread[tid]->noSquashFromTC = false;
614
615 commit.setThreads(thread);
616}
617
618template <class Impl>
619void
620FullO3CPU<Impl>::startup()
621{
622 BaseCPU::startup();
623 for (int tid = 0; tid < numThreads; ++tid)
624 isa[tid]->startup(threadContexts[tid]);
625
626 fetch.startupStage();
627 decode.startupStage();
628 iew.startupStage();
629 rename.startupStage();
630 commit.startupStage();
631}
632
633template <class Impl>
634void
635FullO3CPU<Impl>::activateThread(ThreadID tid)
636{
637 list<ThreadID>::iterator isActive =
638 std::find(activeThreads.begin(), activeThreads.end(), tid);
639
640 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
641 assert(!switchedOut());
642
643 if (isActive == activeThreads.end()) {
644 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
645 tid);
646
647 activeThreads.push_back(tid);
648 }
649}
650
651template <class Impl>
652void
653FullO3CPU<Impl>::deactivateThread(ThreadID tid)
654{
655 //Remove From Active List, if Active
656 list<ThreadID>::iterator thread_it =
657 std::find(activeThreads.begin(), activeThreads.end(), tid);
658
659 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
660 assert(!switchedOut());
661
662 if (thread_it != activeThreads.end()) {
663 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
664 tid);
665 activeThreads.erase(thread_it);
666 }
667
668 fetch.deactivateThread(tid);
669 commit.deactivateThread(tid);
670}
671
672template <class Impl>
673Counter
674FullO3CPU<Impl>::totalInsts() const
675{
676 Counter total(0);
677
678 ThreadID size = thread.size();
679 for (ThreadID i = 0; i < size; i++)
680 total += thread[i]->numInst;
681
682 return total;
683}
684
685template <class Impl>
686Counter
687FullO3CPU<Impl>::totalOps() const
688{
689 Counter total(0);
690
691 ThreadID size = thread.size();
692 for (ThreadID i = 0; i < size; i++)
693 total += thread[i]->numOp;
694
695 return total;
696}
697
698template <class Impl>
699void
700FullO3CPU<Impl>::activateContext(ThreadID tid)
701{
702 assert(!switchedOut());
703
704 // Needs to set each stage to running as well.
705 activateThread(tid);
706
707 // We don't want to wake the CPU if it is drained. In that case,
708 // we just want to flag the thread as active and schedule the tick
709 // event from drainResume() instead.
710 if (getDrainState() == Drainable::Drained)
711 return;
712
713 // If we are time 0 or if the last activation time is in the past,
714 // schedule the next tick and wake up the fetch unit
715 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
716 scheduleTickEvent(Cycles(0));
717
718 // Be sure to signal that there's some activity so the CPU doesn't
719 // deschedule itself.
720 activityRec.activity();
721 fetch.wakeFromQuiesce();
722
723 Cycles cycles(curCycle() - lastRunningCycle);
724 // @todo: This is an oddity that is only here to match the stats
725 if (cycles != 0)
726 --cycles;
727 quiesceCycles += cycles;
728
729 lastActivatedCycle = curTick();
730
731 _status = Running;
732 }
733}
734
735template <class Impl>
736void
737FullO3CPU<Impl>::suspendContext(ThreadID tid)
738{
739 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
740 assert(!switchedOut());
741
742 deactivateThread(tid);
743
744 // If this was the last thread then unschedule the tick event.
745 if (activeThreads.size() == 0)
746 unscheduleTickEvent();
747
748 DPRINTF(Quiesce, "Suspending Context\n");
749 lastRunningCycle = curCycle();
750 _status = Idle;
751}
752
753template <class Impl>
754void
755FullO3CPU<Impl>::haltContext(ThreadID tid)
756{
757 //For now, this is the same as deallocate
758 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
759 assert(!switchedOut());
760
761 deactivateThread(tid);
762 removeThread(tid);
763}
764
765template <class Impl>
766void
767FullO3CPU<Impl>::insertThread(ThreadID tid)
768{
769 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
770 // Will change now that the PC and thread state is internal to the CPU
771 // and not in the ThreadContext.
772 ThreadContext *src_tc;
773 if (FullSystem)
774 src_tc = system->threadContexts[tid];
775 else
776 src_tc = tcBase(tid);
777
778 //Bind Int Regs to Rename Map
779 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
780 PhysRegIndex phys_reg = freeList.getIntReg();
781
782 renameMap[tid].setEntry(ireg,phys_reg);
783 scoreboard.setReg(phys_reg);
784 }
785
786 //Bind Float Regs to Rename Map
787 int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
788 for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
789 PhysRegIndex phys_reg = freeList.getFloatReg();
790
791 renameMap[tid].setEntry(freg,phys_reg);
792 scoreboard.setReg(phys_reg);
793 }
794
795 //Bind condition-code Regs to Rename Map
796 max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
797 for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
798 creg < max_reg; creg++) {
799 PhysRegIndex phys_reg = freeList.getCCReg();
800
801 renameMap[tid].setEntry(creg,phys_reg);
802 scoreboard.setReg(phys_reg);
803 }
804
805 //Copy Thread Data Into RegFile
806 //this->copyFromTC(tid);
807
808 //Set PC/NPC/NNPC
809 pcState(src_tc->pcState(), tid);
810
811 src_tc->setStatus(ThreadContext::Active);
812
813 activateContext(tid);
814
815 //Reset ROB/IQ/LSQ Entries
816 commit.rob->resetEntries();
817 iew.resetEntries();
818}
819
820template <class Impl>
821void
822FullO3CPU<Impl>::removeThread(ThreadID tid)
823{
824 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
825
826 // Copy Thread Data From RegFile
827 // If thread is suspended, it might be re-allocated
828 // this->copyToTC(tid);
829
830
831 // @todo: 2-27-2008: Fix how we free up rename mappings
832 // here to alleviate the case for double-freeing registers
833 // in SMT workloads.
834
835 // Unbind Int Regs from Rename Map
836 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
837 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
838
839 scoreboard.unsetReg(phys_reg);
840 freeList.addReg(phys_reg);
841 }
842
843 // Unbind Float Regs from Rename Map
844 int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
845 for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
846 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
847
848 scoreboard.unsetReg(phys_reg);
849 freeList.addReg(phys_reg);
850 }
851
852 // Unbind condition-code Regs from Rename Map
853 max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
854 for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
855 creg < max_reg; creg++) {
856 PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
857
858 scoreboard.unsetReg(phys_reg);
859 freeList.addReg(phys_reg);
860 }
861
862 // Squash Throughout Pipeline
863 DynInstPtr inst = commit.rob->readHeadInst(tid);
864 InstSeqNum squash_seq_num = inst->seqNum;
865 fetch.squash(0, squash_seq_num, inst, tid);
866 decode.squash(tid);
867 rename.squash(squash_seq_num, tid);
868 iew.squash(tid);
869 iew.ldstQueue.squash(squash_seq_num, tid);
870 commit.rob->squash(squash_seq_num, tid);
871
872
873 assert(iew.instQueue.getCount(tid) == 0);
874 assert(iew.ldstQueue.getCount(tid) == 0);
875
876 // Reset ROB/IQ/LSQ Entries
877
878 // Commented out for now. This should be possible to do by
879 // telling all the pipeline stages to drain first, and then
880 // checking until the drain completes. Once the pipeline is
881 // drained, call resetEntries(). - 10-09-06 ktlim
882/*
883 if (activeThreads.size() >= 1) {
884 commit.rob->resetEntries();
885 iew.resetEntries();
886 }
887*/
888}
889
890template <class Impl>
891Fault
892FullO3CPU<Impl>::hwrei(ThreadID tid)
893{
894#if THE_ISA == ALPHA_ISA
895 // Need to clear the lock flag upon returning from an interrupt.
896 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
897
898 this->thread[tid]->kernelStats->hwrei();
899
900 // FIXME: XXX check for interrupts? XXX
901#endif
902 return NoFault;
903}
904
905template <class Impl>
906bool
907FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
908{
909#if THE_ISA == ALPHA_ISA
910 if (this->thread[tid]->kernelStats)
911 this->thread[tid]->kernelStats->callpal(palFunc,
912 this->threadContexts[tid]);
913
914 switch (palFunc) {
915 case PAL::halt:
916 halt();
917 if (--System::numSystemsRunning == 0)
918 exitSimLoop("all cpus halted");
919 break;
920
921 case PAL::bpt:
922 case PAL::bugchk:
923 if (this->system->breakpoint())
924 return false;
925 break;
926 }
927#endif
928 return true;
929}
930
931template <class Impl>
932Fault
933FullO3CPU<Impl>::getInterrupts()
934{
935 // Check if there are any outstanding interrupts
936 return this->interrupts->getInterrupt(this->threadContexts[0]);
937}
938
939template <class Impl>
940void
941FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
942{
943 // Check for interrupts here. For now can copy the code that
944 // exists within isa_fullsys_traits.hh. Also assume that thread 0
945 // is the one that handles the interrupts.
946 // @todo: Possibly consolidate the interrupt checking code.
947 // @todo: Allow other threads to handle interrupts.
948
949 assert(interrupt != NoFault);
950 this->interrupts->updateIntrInfo(this->threadContexts[0]);
951
952 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
953 this->trap(interrupt, 0, nullptr);
954}
955
956template <class Impl>
957void
958FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
959 const StaticInstPtr &inst)
960{
961 // Pass the thread's TC into the invoke method.
962 fault->invoke(this->threadContexts[tid], inst);
963}
964
965template <class Impl>
966void
967FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
968{
969 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
970
971 DPRINTF(Activity,"Activity: syscall() called.\n");
972
973 // Temporarily increase this by one to account for the syscall
974 // instruction.
975 ++(this->thread[tid]->funcExeInst);
976
977 // Execute the actual syscall.
978 this->thread[tid]->syscall(callnum);
979
980 // Decrease funcExeInst by one as the normal commit will handle
981 // incrementing it.
982 --(this->thread[tid]->funcExeInst);
983}
984
985template <class Impl>
986void
987FullO3CPU<Impl>::serializeThread(std::ostream &os, ThreadID tid)
988{
989 thread[tid]->serialize(os);
990}
991
992template <class Impl>
993void
994FullO3CPU<Impl>::unserializeThread(Checkpoint *cp, const std::string §ion,
995 ThreadID tid)
996{
997 thread[tid]->unserialize(cp, section);
998}
999
1000template <class Impl>
1001unsigned int
1002FullO3CPU<Impl>::drain(DrainManager *drain_manager)
1003{
1004 // If the CPU isn't doing anything, then return immediately.
1005 if (switchedOut()) {
1006 setDrainState(Drainable::Drained);
1007 return 0;
1008 }
1009
1010 DPRINTF(Drain, "Draining...\n");
1011 setDrainState(Drainable::Draining);
1012
1013 // We only need to signal a drain to the commit stage as this
1014 // initiates squashing controls the draining. Once the commit
1015 // stage commits an instruction where it is safe to stop, it'll
1016 // squash the rest of the instructions in the pipeline and force
1017 // the fetch stage to stall. The pipeline will be drained once all
1018 // in-flight instructions have retired.
1019 commit.drain();
1020
1021 // Wake the CPU and record activity so everything can drain out if
1022 // the CPU was not able to immediately drain.
1023 if (!isDrained()) {
1024 drainManager = drain_manager;
1025
1026 wakeCPU();
1027 activityRec.activity();
1028
1029 DPRINTF(Drain, "CPU not drained\n");
1030
1031 return 1;
1032 } else {
1033 setDrainState(Drainable::Drained);
1034 DPRINTF(Drain, "CPU is already drained\n");
1035 if (tickEvent.scheduled())
1036 deschedule(tickEvent);
1037
1038 // Flush out any old data from the time buffers. In
1039 // particular, there might be some data in flight from the
1040 // fetch stage that isn't visible in any of the CPU buffers we
1041 // test in isDrained().
1042 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1043 timeBuffer.advance();
1044 fetchQueue.advance();
1045 decodeQueue.advance();
1046 renameQueue.advance();
1047 iewQueue.advance();
1048 }
1049
1050 drainSanityCheck();
1051 return 0;
1052 }
1053}
1054
1055template <class Impl>
1056bool
1057FullO3CPU<Impl>::tryDrain()
1058{
1059 if (!drainManager || !isDrained())
1060 return false;
1061
1062 if (tickEvent.scheduled())
1063 deschedule(tickEvent);
1064
1065 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1066 drainManager->signalDrainDone();
1067 drainManager = NULL;
1068
1069 return true;
1070}
1071
1072template <class Impl>
1073void
1074FullO3CPU<Impl>::drainSanityCheck() const
1075{
1076 assert(isDrained());
1077 fetch.drainSanityCheck();
1078 decode.drainSanityCheck();
1079 rename.drainSanityCheck();
1080 iew.drainSanityCheck();
1081 commit.drainSanityCheck();
1082}
1083
1084template <class Impl>
1085bool
1086FullO3CPU<Impl>::isDrained() const
1087{
1088 bool drained(true);
1089
1090 if (!instList.empty() || !removeList.empty()) {
1091 DPRINTF(Drain, "Main CPU structures not drained.\n");
1092 drained = false;
1093 }
1094
1095 if (!fetch.isDrained()) {
1096 DPRINTF(Drain, "Fetch not drained.\n");
1097 drained = false;
1098 }
1099
1100 if (!decode.isDrained()) {
1101 DPRINTF(Drain, "Decode not drained.\n");
1102 drained = false;
1103 }
1104
1105 if (!rename.isDrained()) {
1106 DPRINTF(Drain, "Rename not drained.\n");
1107 drained = false;
1108 }
1109
1110 if (!iew.isDrained()) {
1111 DPRINTF(Drain, "IEW not drained.\n");
1112 drained = false;
1113 }
1114
1115 if (!commit.isDrained()) {
1116 DPRINTF(Drain, "Commit not drained.\n");
1117 drained = false;
1118 }
1119
1120 return drained;
1121}
1122
1123template <class Impl>
1124void
1125FullO3CPU<Impl>::commitDrained(ThreadID tid)
1126{
1127 fetch.drainStall(tid);
1128}
1129
1130template <class Impl>
1131void
1132FullO3CPU<Impl>::drainResume()
1133{
1134 setDrainState(Drainable::Running);
1135 if (switchedOut())
1136 return;
1137
1138 DPRINTF(Drain, "Resuming...\n");
1139 verifyMemoryMode();
1140
1141 fetch.drainResume();
1142 commit.drainResume();
1143
1144 _status = Idle;
1145 for (ThreadID i = 0; i < thread.size(); i++) {
1146 if (thread[i]->status() == ThreadContext::Active) {
1147 DPRINTF(Drain, "Activating thread: %i\n", i);
1148 activateThread(i);
1149 _status = Running;
1150 }
1151 }
1152
1153 assert(!tickEvent.scheduled());
1154 if (_status == Running)
1155 schedule(tickEvent, nextCycle());
1156}
1157
1158template <class Impl>
1159void
1160FullO3CPU<Impl>::switchOut()
1161{
1162 DPRINTF(O3CPU, "Switching out\n");
1163 BaseCPU::switchOut();
1164
1165 activityRec.reset();
1166
1167 _status = SwitchedOut;
1168
1169 if (checker)
1170 checker->switchOut();
1171}
1172
1173template <class Impl>
1174void
1175FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1176{
1177 BaseCPU::takeOverFrom(oldCPU);
1178
1179 fetch.takeOverFrom();
1180 decode.takeOverFrom();
1181 rename.takeOverFrom();
1182 iew.takeOverFrom();
1183 commit.takeOverFrom();
1184
1185 assert(!tickEvent.scheduled());
1186
1187 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1188 if (oldO3CPU)
1189 globalSeqNum = oldO3CPU->globalSeqNum;
1190
1191 lastRunningCycle = curCycle();
1192 _status = Idle;
1193}
1194
1195template <class Impl>
1196void
1197FullO3CPU<Impl>::verifyMemoryMode() const
1198{
1199 if (!system->isTimingMode()) {
1200 fatal("The O3 CPU requires the memory system to be in "
1201 "'timing' mode.\n");
1202 }
1203}
1204
1205template <class Impl>
1206TheISA::MiscReg
1207FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1208{
1209 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1210}
1211
1212template <class Impl>
1213TheISA::MiscReg
1214FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1215{
1216 miscRegfileReads++;
1217 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1218}
1219
1220template <class Impl>
1221void
1222FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1223 const TheISA::MiscReg &val, ThreadID tid)
1224{
1225 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1226}
1227
1228template <class Impl>
1229void
1230FullO3CPU<Impl>::setMiscReg(int misc_reg,
1231 const TheISA::MiscReg &val, ThreadID tid)
1232{
1233 miscRegfileWrites++;
1234 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1235}
1236
1237template <class Impl>
1238uint64_t
1239FullO3CPU<Impl>::readIntReg(int reg_idx)
1240{
1241 intRegfileReads++;
1242 return regFile.readIntReg(reg_idx);
1243}
1244
1245template <class Impl>
1246FloatReg
1247FullO3CPU<Impl>::readFloatReg(int reg_idx)
1248{
1249 fpRegfileReads++;
1250 return regFile.readFloatReg(reg_idx);
1251}
1252
1253template <class Impl>
1254FloatRegBits
1255FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1256{
1257 fpRegfileReads++;
1258 return regFile.readFloatRegBits(reg_idx);
1259}
1260
1261template <class Impl>
1262CCReg
1263FullO3CPU<Impl>::readCCReg(int reg_idx)
1264{
1265 ccRegfileReads++;
1266 return regFile.readCCReg(reg_idx);
1267}
1268
1269template <class Impl>
1270void
1271FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1272{
1273 intRegfileWrites++;
1274 regFile.setIntReg(reg_idx, val);
1275}
1276
1277template <class Impl>
1278void
1279FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1280{
1281 fpRegfileWrites++;
1282 regFile.setFloatReg(reg_idx, val);
1283}
1284
1285template <class Impl>
1286void
1287FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1288{
1289 fpRegfileWrites++;
1290 regFile.setFloatRegBits(reg_idx, val);
1291}
1292
1293template <class Impl>
1294void
1295FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
1296{
1297 ccRegfileWrites++;
1298 regFile.setCCReg(reg_idx, val);
1299}
1300
1301template <class Impl>
1302uint64_t
1303FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1304{
1305 intRegfileReads++;
1306 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1307
1308 return regFile.readIntReg(phys_reg);
1309}
1310
1311template <class Impl>
1312float
1313FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1314{
1315 fpRegfileReads++;
1316 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1317
1318 return regFile.readFloatReg(phys_reg);
1319}
1320
1321template <class Impl>
1322uint64_t
1323FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1324{
1325 fpRegfileReads++;
1326 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1327
1328 return regFile.readFloatRegBits(phys_reg);
1329}
1330
1331template <class Impl>
1332CCReg
1333FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1334{
1335 ccRegfileReads++;
1336 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1337
1338 return regFile.readCCReg(phys_reg);
1339}
1340
1341template <class Impl>
1342void
1343FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1344{
1345 intRegfileWrites++;
1346 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1347
1348 regFile.setIntReg(phys_reg, val);
1349}
1350
1351template <class Impl>
1352void
1353FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1354{
1355 fpRegfileWrites++;
1356 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1357
1358 regFile.setFloatReg(phys_reg, val);
1359}
1360
1361template <class Impl>
1362void
1363FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1364{
1365 fpRegfileWrites++;
1366 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1367
1368 regFile.setFloatRegBits(phys_reg, val);
1369}
1370
1371template <class Impl>
1372void
1373FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1374{
1375 ccRegfileWrites++;
1376 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1377
1378 regFile.setCCReg(phys_reg, val);
1379}
1380
1381template <class Impl>
1382TheISA::PCState
1383FullO3CPU<Impl>::pcState(ThreadID tid)
1384{
1385 return commit.pcState(tid);
1386}
1387
1388template <class Impl>
1389void
1390FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1391{
1392 commit.pcState(val, tid);
1393}
1394
1395template <class Impl>
1396Addr
1397FullO3CPU<Impl>::instAddr(ThreadID tid)
1398{
1399 return commit.instAddr(tid);
1400}
1401
1402template <class Impl>
1403Addr
1404FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1405{
1406 return commit.nextInstAddr(tid);
1407}
1408
1409template <class Impl>
1410MicroPC
1411FullO3CPU<Impl>::microPC(ThreadID tid)
1412{
1413 return commit.microPC(tid);
1414}
1415
1416template <class Impl>
1417void
1418FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1419{
1420 this->thread[tid]->noSquashFromTC = true;
1421 this->commit.generateTCEvent(tid);
1422}
1423
1424template <class Impl>
1425typename FullO3CPU<Impl>::ListIt
1426FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1427{
1428 instList.push_back(inst);
1429
1430 return --(instList.end());
1431}
1432
1433template <class Impl>
1434void
1435FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1436{
1437 // Keep an instruction count.
1438 if (!inst->isMicroop() || inst->isLastMicroop()) {
1439 thread[tid]->numInst++;
1440 thread[tid]->numInsts++;
1441 committedInsts[tid]++;
1442 }
1443 thread[tid]->numOp++;
1444 thread[tid]->numOps++;
1445 committedOps[tid]++;
1446
1447 system->totalNumInsts++;
1448 // Check for instruction-count-based events.
1449 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1450 system->instEventQueue.serviceEvents(system->totalNumInsts);
1451
1452 probeInstCommit(inst->staticInst);
1453}
1454
1455template <class Impl>
1456void
1457FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1458{
1459 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1460 "[sn:%lli]\n",
1461 inst->threadNumber, inst->pcState(), inst->seqNum);
1462
1463 removeInstsThisCycle = true;
1464
1465 // Remove the front instruction.
1466 removeList.push(inst->getInstListIt());
1467}
1468
1469template <class Impl>
1470void
1471FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1472{
1473 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1474 " list.\n", tid);
1475
1476 ListIt end_it;
1477
1478 bool rob_empty = false;
1479
1480 if (instList.empty()) {
1481 return;
1482 } else if (rob.isEmpty(tid)) {
1483 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1484 end_it = instList.begin();
1485 rob_empty = true;
1486 } else {
1487 end_it = (rob.readTailInst(tid))->getInstListIt();
1488 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1489 }
1490
1491 removeInstsThisCycle = true;
1492
1493 ListIt inst_it = instList.end();
1494
1495 inst_it--;
1496
1497 // Walk through the instruction list, removing any instructions
1498 // that were inserted after the given instruction iterator, end_it.
1499 while (inst_it != end_it) {
1500 assert(!instList.empty());
1501
1502 squashInstIt(inst_it, tid);
1503
1504 inst_it--;
1505 }
1506
1507 // If the ROB was empty, then we actually need to remove the first
1508 // instruction as well.
1509 if (rob_empty) {
1510 squashInstIt(inst_it, tid);
1511 }
1512}
1513
1514template <class Impl>
1515void
1516FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1517{
1518 assert(!instList.empty());
1519
1520 removeInstsThisCycle = true;
1521
1522 ListIt inst_iter = instList.end();
1523
1524 inst_iter--;
1525
1526 DPRINTF(O3CPU, "Deleting instructions from instruction "
1527 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1528 tid, seq_num, (*inst_iter)->seqNum);
1529
1530 while ((*inst_iter)->seqNum > seq_num) {
1531
1532 bool break_loop = (inst_iter == instList.begin());
1533
1534 squashInstIt(inst_iter, tid);
1535
1536 inst_iter--;
1537
1538 if (break_loop)
1539 break;
1540 }
1541}
1542
1543template <class Impl>
1544inline void
1545FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1546{
1547 if ((*instIt)->threadNumber == tid) {
1548 DPRINTF(O3CPU, "Squashing instruction, "
1549 "[tid:%i] [sn:%lli] PC %s\n",
1550 (*instIt)->threadNumber,
1551 (*instIt)->seqNum,
1552 (*instIt)->pcState());
1553
1554 // Mark it as squashed.
1555 (*instIt)->setSquashed();
1556
1557 // @todo: Formulate a consistent method for deleting
1558 // instructions from the instruction list
1559 // Remove the instruction from the list.
1560 removeList.push(instIt);
1561 }
1562}
1563
1564template <class Impl>
1565void
1566FullO3CPU<Impl>::cleanUpRemovedInsts()
1567{
1568 while (!removeList.empty()) {
1569 DPRINTF(O3CPU, "Removing instruction, "
1570 "[tid:%i] [sn:%lli] PC %s\n",
1571 (*removeList.front())->threadNumber,
1572 (*removeList.front())->seqNum,
1573 (*removeList.front())->pcState());
1574
1575 instList.erase(removeList.front());
1576
1577 removeList.pop();
1578 }
1579
1580 removeInstsThisCycle = false;
1581}
1582/*
1583template <class Impl>
1584void
1585FullO3CPU<Impl>::removeAllInsts()
1586{
1587 instList.clear();
1588}
1589*/
1590template <class Impl>
1591void
1592FullO3CPU<Impl>::dumpInsts()
1593{
1594 int num = 0;
1595
1596 ListIt inst_list_it = instList.begin();
1597
1598 cprintf("Dumping Instruction List\n");
1599
1600 while (inst_list_it != instList.end()) {
1601 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1602 "Squashed:%i\n\n",
1603 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1604 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1605 (*inst_list_it)->isSquashed());
1606 inst_list_it++;
1607 ++num;
1608 }
1609}
1610/*
1611template <class Impl>
1612void
1613FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1614{
1615 iew.wakeDependents(inst);
1616}
1617*/
1618template <class Impl>
1619void
1620FullO3CPU<Impl>::wakeCPU()
1621{
1622 if (activityRec.active() || tickEvent.scheduled()) {
1623 DPRINTF(Activity, "CPU already running.\n");
1624 return;
1625 }
1626
1627 DPRINTF(Activity, "Waking up CPU\n");
1628
1629 Cycles cycles(curCycle() - lastRunningCycle);
1630 // @todo: This is an oddity that is only here to match the stats
1631 if (cycles > 1) {
1632 --cycles;
1633 idleCycles += cycles;
1634 numCycles += cycles;
1635 ppCycles->notify(cycles);
1636 }
1637
1638 schedule(tickEvent, clockEdge());
1639}
1640
1641template <class Impl>
1642void
1643FullO3CPU<Impl>::wakeup()
1644{
1645 if (this->thread[0]->status() != ThreadContext::Suspended)
1646 return;
1647
1648 this->wakeCPU();
1649
1650 DPRINTF(Quiesce, "Suspended Processor woken\n");
1651 this->threadContexts[0]->activate();
1652}
1653
1654template <class Impl>
1655ThreadID
1656FullO3CPU<Impl>::getFreeTid()
1657{
1658 for (ThreadID tid = 0; tid < numThreads; tid++) {
1659 if (!tids[tid]) {
1660 tids[tid] = true;
1661 return tid;
1662 }
1663 }
1664
1665 return InvalidThreadID;
1666}
1667
1668template <class Impl>
1669void
1670FullO3CPU<Impl>::updateThreadPriority()
1671{
1672 if (activeThreads.size() > 1) {
1673 //DEFAULT TO ROUND ROBIN SCHEME
1674 //e.g. Move highest priority to end of thread list
1675 list<ThreadID>::iterator list_begin = activeThreads.begin();
1676
1677 unsigned high_thread = *list_begin;
1678
1679 activeThreads.erase(list_begin);
1680
1681 activeThreads.push_back(high_thread);
1682 }
1683}
1684
1685// Forward declaration of FullO3CPU.
1686template class FullO3CPU<O3CPUImpl>;