1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 211 unchanged lines hidden (view full) ---

220 removeInstsThisCycle(false),
221 fetch(this, params),
222 decode(this, params),
223 rename(this, params),
224 iew(this, params),
225 commit(this, params),
226
227 regFile(params->numPhysIntRegs,
228 params->numPhysFloatRegs),
229
230 freeList(name() + ".freelist", &regFile),
231
232 rob(this,
233 params->numROBEntries, params->squashWidth,
234 params->smtROBPolicy, params->smtROBThreshold,
235 params->numThreads),
236

--- 85 unchanged lines hidden (view full) ---

322 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
323 "or edit your workload size.");
324 }
325 }
326
327 //Make Sure That this a Valid Architeture
328 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
329 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
330
331 rename.setScoreboard(&scoreboard);
332 iew.setScoreboard(&scoreboard);
333
334 // Setup the rename map for whichever stages need it.
335 for (ThreadID tid = 0; tid < numThreads; tid++) {
336 isa[tid] = params->isa[tid];
337

--- 25 unchanged lines hidden (view full) ---

363 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
364 }
365
366 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
367 PhysRegIndex phys_reg = freeList.getFloatReg();
368 renameMap[tid].setFloatEntry(ridx, phys_reg);
369 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
370 }
371 }
372
373 rename.setRenameMap(renameMap);
374 commit.setRenameMap(commitRenameMap);
375 rename.setFreeList(&freeList);
376
377 // Setup the ROB for whichever stages need it.
378 commit.setROB(&rob);

--- 171 unchanged lines hidden (view full) ---

550 .desc("number of floating regfile reads")
551 .prereq(fpRegfileReads);
552
553 fpRegfileWrites
554 .name(name() + ".fp_regfile_writes")
555 .desc("number of floating regfile writes")
556 .prereq(fpRegfileWrites);
557
558 miscRegfileReads
559 .name(name() + ".misc_regfile_reads")
560 .desc("number of misc regfile reads")
561 .prereq(miscRegfileReads);
562
563 miscRegfileWrites
564 .name(name() + ".misc_regfile_writes")
565 .desc("number of misc regfile writes")

--- 271 unchanged lines hidden (view full) ---

837 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
838 PhysRegIndex phys_reg = freeList.getIntReg();
839
840 renameMap[tid].setEntry(ireg,phys_reg);
841 scoreboard.setReg(phys_reg);
842 }
843
844 //Bind Float Regs to Rename Map
845 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
846 PhysRegIndex phys_reg = freeList.getFloatReg();
847
848 renameMap[tid].setEntry(freg,phys_reg);
849 scoreboard.setReg(phys_reg);
850 }
851
852 //Copy Thread Data Into RegFile
853 //this->copyFromTC(tid);
854
855 //Set PC/NPC/NNPC
856 pcState(src_tc->pcState(), tid);
857
858 src_tc->setStatus(ThreadContext::Active);
859

--- 23 unchanged lines hidden (view full) ---

883 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
884 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
885
886 scoreboard.unsetReg(phys_reg);
887 freeList.addReg(phys_reg);
888 }
889
890 // Unbind Float Regs from Rename Map
891 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
892 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
893
894 scoreboard.unsetReg(phys_reg);
895 freeList.addReg(phys_reg);
896 }
897
898 // Squash Throughout Pipeline
899 DynInstPtr inst = commit.rob->readHeadInst(tid);
900 InstSeqNum squash_seq_num = inst->seqNum;
901 fetch.squash(0, squash_seq_num, inst, tid);
902 decode.squash(tid);
903 rename.squash(squash_seq_num, tid);
904 iew.squash(tid);
905 iew.ldstQueue.squash(squash_seq_num, tid);

--- 23 unchanged lines hidden (view full) ---

929FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
930{
931 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
932 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
933 tid);
934
935 bool ready = true;
936
937 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
938 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
939 "Phys. Int. Regs.\n",
940 tid);
941 ready = false;
942 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
943 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
944 "Phys. Float. Regs.\n",
945 tid);
946 ready = false;
947 } else if (commit.rob->numFreeEntries() >=
948 commit.rob->entryAmount(activeThreads.size() + 1)) {
949 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
950 "ROB entries.\n",
951 tid);
952 ready = false;
953 } else if (iew.instQueue.numFreeEntries() >=
954 iew.instQueue.entryAmount(activeThreads.size() + 1)) {

--- 406 unchanged lines hidden (view full) ---

1361FloatRegBits
1362FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1363{
1364 fpRegfileReads++;
1365 return regFile.readFloatRegBits(reg_idx);
1366}
1367
1368template <class Impl>
1369void
1370FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1371{
1372 intRegfileWrites++;
1373 regFile.setIntReg(reg_idx, val);
1374}
1375
1376template <class Impl>

--- 8 unchanged lines hidden (view full) ---

1385void
1386FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1387{
1388 fpRegfileWrites++;
1389 regFile.setFloatRegBits(reg_idx, val);
1390}
1391
1392template <class Impl>
1393uint64_t
1394FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1395{
1396 intRegfileReads++;
1397 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1398
1399 return regFile.readIntReg(phys_reg);
1400}

--- 14 unchanged lines hidden (view full) ---

1415{
1416 fpRegfileReads++;
1417 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1418
1419 return regFile.readFloatRegBits(phys_reg);
1420}
1421
1422template <class Impl>
1423void
1424FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1425{
1426 intRegfileWrites++;
1427 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1428
1429 regFile.setIntReg(phys_reg, val);
1430}

--- 14 unchanged lines hidden (view full) ---

1445{
1446 fpRegfileWrites++;
1447 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1448
1449 regFile.setFloatRegBits(phys_reg, val);
1450}
1451
1452template <class Impl>
1453TheISA::PCState
1454FullO3CPU<Impl>::pcState(ThreadID tid)
1455{
1456 return commit.pcState(tid);
1457}
1458
1459template <class Impl>
1460void

--- 312 unchanged lines hidden ---