1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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433 .prereq(timesIdled);
434
435 idleCycles
436 .name(name() + ".idleCycles")
437 .desc("Total number of cycles that the CPU has spent unscheduled due "
438 "to idling")
439 .prereq(idleCycles);
440
441 // Number of Instructions simulated
442 // --------------------------------
443 // Should probably be in Base CPU but need templated
444 // MaxThreads so put in here instead
445 committedInsts
446 .init(numThreads)
447 .name(name() + ".committedInsts")
448 .desc("Number of Instructions Simulated");

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677 if (lastActivatedCycle < curTick()) {
678 scheduleTickEvent(delay);
679
680 // Be sure to signal that there's some activity so the CPU doesn't
681 // deschedule itself.
682 activityRec.activity();
683 fetch.wakeFromQuiesce();
684
685 lastActivatedCycle = curTick();
686
687 _status = Running;
688 }
689}
690
691template <class Impl>
692bool

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711FullO3CPU<Impl>::suspendContext(ThreadID tid)
712{
713 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
714 bool deallocated = deallocateContext(tid, false, 1);
715 // If this was the last thread then unschedule the tick event.
716 if ((activeThreads.size() == 1 && !deallocated) ||
717 activeThreads.size() == 0)
718 unscheduleTickEvent();
719 _status = Idle;
720}
721
722template <class Impl>
723void
724FullO3CPU<Impl>::haltContext(ThreadID tid)
725{
726 //For now, this is the same as deallocate

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1188 ThreadContext *tc = threadContexts[i];
1189 if (tc->status() == ThreadContext::Active && _status != Running) {
1190 _status = Running;
1191 reschedule(tickEvent, nextCycle(), true);
1192 }
1193 }
1194 if (!tickEvent.scheduled())
1195 schedule(tickEvent, nextCycle());
1196}
1197
1198template <class Impl>
1199TheISA::MiscReg
1200FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1201{
1202 return this->isa[tid].readMiscRegNoEffect(misc_reg);
1203}

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