1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;

--- 41 unchanged lines hidden (view full) ---

63#if FULL_SYSTEM
64#include "cpu/quiesce_event.hh"
65#else
66#include "sim/process.hh"
67#endif
68
69#if USE_CHECKER
70#include "cpu/checker/cpu.hh"
71#include "cpu/checker/thread_context.hh"
72#endif
73
74#if THE_ISA == ALPHA_ISA
75#include "arch/alpha/osfpal.hh"
76#include "debug/Activity.hh"
77#endif
78
79struct BaseCPUParams;
80
81using namespace TheISA;
82using namespace std;
83
84BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
85 : BaseCPU(params)
86{
87}
88
89void
90BaseO3CPU::regStats()
91{
92 BaseCPU::regStats();
93}
94
95template<class Impl>
96bool
97FullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt)
98{
99 DPRINTF(O3CPU, "Fetch unit received timing\n");
100 if (pkt->isResponse()) {
101 // We shouldn't ever get a block in ownership state
102 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
103
104 fetch->processCacheCompletion(pkt);
105 }
106 //else Snooped a coherence request, just return
107 return true;
108}
109
110template<class Impl>
111void
112FullO3CPU<Impl>::IcachePort::recvRetry()
113{
114 fetch->recvRetry();
115}
116
117template <class Impl>
118bool
119FullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt)
120{
121 return lsq->recvTiming(pkt);
122}
123
124template <class Impl>
125void
126FullO3CPU<Impl>::DcachePort::recvRetry()
127{
128 lsq->recvRetry();
129}
130
131template <class Impl>
132FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
133 : Event(CPU_Tick_Pri), cpu(c)
134{
135}
136
137template <class Impl>
138void
139FullO3CPU<Impl>::TickEvent::process()

--- 98 unchanged lines hidden (view full) ---

238 params->numThreads),
239
240 scoreboard(params->numThreads,
241 TheISA::NumIntRegs, params->numPhysIntRegs,
242 TheISA::NumFloatRegs, params->numPhysFloatRegs,
243 TheISA::NumMiscRegs * numThreads,
244 TheISA::ZeroReg),
245
246 icachePort(&fetch, this),
247 dcachePort(&iew.ldstQueue, this),
248
249 timeBuffer(params->backComSize, params->forwardComSize),
250 fetchQueue(params->backComSize, params->forwardComSize),
251 decodeQueue(params->backComSize, params->forwardComSize),
252 renameQueue(params->backComSize, params->forwardComSize),
253 iewQueue(params->backComSize, params->forwardComSize),
254 activityRec(name(), NumStages,
255 params->backComSize + params->forwardComSize,
256 params->activity),

--- 7 unchanged lines hidden (view full) ---

264 _status = Running;
265 } else {
266 _status = Idle;
267 }
268
269#if USE_CHECKER
270 if (params->checker) {
271 BaseCPU *temp_checker = params->checker;
272 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
273 checker->setIcachePort(&icachePort);
274#if FULL_SYSTEM
275 checker->setSystem(params->system);
276#endif
277 } else {
278 checker = NULL;
279 }
280#endif // USE_CHECKER
281

--- 123 unchanged lines hidden (view full) ---

405
406 // Setup any thread state.
407 this->thread.resize(this->numThreads);
408
409 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
410#if FULL_SYSTEM
411 // SMT is not supported in FS mode yet.
412 assert(this->numThreads == 1);
413 this->thread[tid] = new Thread(this, 0);
414#else
415 if (tid < params->workload.size()) {
416 DPRINTF(O3CPU, "Workload[%i] process is %#x",
417 tid, this->thread[tid]);
418 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
419 (typename Impl::O3CPU *)(this),
420 tid, params->workload[tid]);
421

--- 68 unchanged lines hidden (view full) ---

490 .prereq(timesIdled);
491
492 idleCycles
493 .name(name() + ".idleCycles")
494 .desc("Total number of cycles that the CPU has spent unscheduled due "
495 "to idling")
496 .prereq(idleCycles);
497
498 quiesceCycles
499 .name(name() + ".quiesceCycles")
500 .desc("Total number of cycles that CPU has spent quiesced or waiting "
501 "for an interrupt")
502 .prereq(quiesceCycles);
503
504 // Number of Instructions simulated
505 // --------------------------------
506 // Should probably be in Base CPU but need templated
507 // MaxThreads so put in here instead
508 committedInsts
509 .init(numThreads)
510 .name(name() + ".committedInsts")
511 .desc("Number of Instructions Simulated");

--- 64 unchanged lines hidden (view full) ---

576 .prereq(miscRegfileWrites);
577}
578
579template <class Impl>
580Port *
581FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
582{
583 if (if_name == "dcache_port")
584 return &dcachePort;
585 else if (if_name == "icache_port")
586 return &icachePort;
587 else
588 panic("No Such Port\n");
589}
590
591template <class Impl>
592void
593FullO3CPU<Impl>::tick()
594{

--- 59 unchanged lines hidden (view full) ---

654{
655 BaseCPU::init();
656
657 // Set inSyscall so that the CPU doesn't squash when initially
658 // setting up registers.
659 for (ThreadID tid = 0; tid < numThreads; ++tid)
660 thread[tid]->inSyscall = true;
661
662 // this CPU could still be unconnected if we are restoring from a
663 // checkpoint and this CPU is to be switched in, thus we can only
664 // do this here if the instruction port is actually connected, if
665 // not we have to do it as part of takeOverFrom
666 if (icachePort.isConnected())
667 fetch.setIcache();
668
669#if FULL_SYSTEM
670 for (ThreadID tid = 0; tid < numThreads; tid++) {
671 ThreadContext *src_tc = threadContexts[tid];
672 TheISA::initCPU(src_tc, src_tc->contextId());
673 // Initialise the ThreadContext's memory proxies
674 thread[tid]->initMemProxies(thread[tid]->getTC());
675 }
676#endif
677
678 // Clear inSyscall.
679 for (int tid = 0; tid < numThreads; ++tid)
680 thread[tid]->inSyscall = false;
681
682 // Initialize stages.

--- 68 unchanged lines hidden (view full) ---

751 if (lastActivatedCycle < curTick()) {
752 scheduleTickEvent(delay);
753
754 // Be sure to signal that there's some activity so the CPU doesn't
755 // deschedule itself.
756 activityRec.activity();
757 fetch.wakeFromQuiesce();
758
759 quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
760
761 lastActivatedCycle = curTick();
762
763 _status = Running;
764 }
765}
766
767template <class Impl>
768bool
769FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove,
770 int delay)
771{
772 // Schedule removal of thread data from CPU
773 if (delay){
774 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
775 "on cycle %d\n", tid, curTick() + ticks(delay));
776 scheduleDeallocateContextEvent(tid, remove, delay);
777 return false;
778 } else {

--- 4 unchanged lines hidden (view full) ---

783 }
784}
785
786template <class Impl>
787void
788FullO3CPU<Impl>::suspendContext(ThreadID tid)
789{
790 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
791 bool deallocated = scheduleDeallocateContext(tid, false, 1);
792 // If this was the last thread then unschedule the tick event.
793 if ((activeThreads.size() == 1 && !deallocated) ||
794 activeThreads.size() == 0)
795 unscheduleTickEvent();
796
797 DPRINTF(Quiesce, "Suspending Context\n");
798 lastRunningCycle = curTick();
799 _status = Idle;
800}
801
802template <class Impl>
803void
804FullO3CPU<Impl>::haltContext(ThreadID tid)
805{
806 //For now, this is the same as deallocate
807 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
808 scheduleDeallocateContext(tid, true, 1);
809}
810
811template <class Impl>
812void
813FullO3CPU<Impl>::insertThread(ThreadID tid)
814{
815 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
816 // Will change now that the PC and thread state is internal to the CPU

--- 215 unchanged lines hidden (view full) ---

1032
1033 assert(interrupt != NoFault);
1034 this->interrupts->updateIntrInfo(this->threadContexts[0]);
1035
1036 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
1037 this->trap(interrupt, 0, NULL);
1038}
1039
1040#endif
1041
1042template <class Impl>
1043void
1044FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
1045{
1046 // Pass the thread's TC into the invoke method.
1047 fault->invoke(this->threadContexts[tid], inst);

--- 178 unchanged lines hidden (view full) ---

1226 fetchQueue.advance();
1227 decodeQueue.advance();
1228 renameQueue.advance();
1229 iewQueue.advance();
1230 }
1231
1232 activityRec.reset();
1233
1234 BaseCPU::takeOverFrom(oldCPU);
1235
1236 fetch.takeOverFrom();
1237 decode.takeOverFrom();
1238 rename.takeOverFrom();
1239 iew.takeOverFrom();
1240 commit.takeOverFrom();
1241
1242 assert(!tickEvent.scheduled() || tickEvent.squashed());

--- 21 unchanged lines hidden (view full) ---

1264 ThreadContext *tc = threadContexts[i];
1265 if (tc->status() == ThreadContext::Active && _status != Running) {
1266 _status = Running;
1267 reschedule(tickEvent, nextCycle(), true);
1268 }
1269 }
1270 if (!tickEvent.scheduled())
1271 schedule(tickEvent, nextCycle());
1272
1273 lastRunningCycle = curTick();
1274}
1275
1276template <class Impl>
1277TheISA::MiscReg
1278FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1279{
1280 return this->isa[tid].readMiscRegNoEffect(misc_reg);
1281}

--- 432 unchanged lines hidden (view full) ---

1714template <class Impl>
1715void
1716FullO3CPU<Impl>::updateThreadPriority()
1717{
1718 if (activeThreads.size() > 1) {
1719 //DEFAULT TO ROUND ROBIN SCHEME
1720 //e.g. Move highest priority to end of thread list
1721 list<ThreadID>::iterator list_begin = activeThreads.begin();
1722
1723 unsigned high_thread = *list_begin;
1724
1725 activeThreads.erase(list_begin);
1726
1727 activeThreads.push_back(high_thread);
1728 }
1729}
1730
1731// Forward declaration of FullO3CPU.
1732template class FullO3CPU<O3CPUImpl>;