1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;

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74}
75
76void
77BaseO3CPU::regStats()
78{
79 BaseCPU::regStats();
80}
81
82template <class Impl>
83FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
84 : Event(CPU_Tick_Pri), cpu(c)
85{
86}
87
88template <class Impl>
89void
90FullO3CPU<Impl>::TickEvent::process()

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189 params->numThreads),
190
191 scoreboard(params->numThreads,
192 TheISA::NumIntRegs, params->numPhysIntRegs,
193 TheISA::NumFloatRegs, params->numPhysFloatRegs,
194 TheISA::NumMiscRegs * numThreads,
195 TheISA::ZeroReg),
196
197 timeBuffer(params->backComSize, params->forwardComSize),
198 fetchQueue(params->backComSize, params->forwardComSize),
199 decodeQueue(params->backComSize, params->forwardComSize),
200 renameQueue(params->backComSize, params->forwardComSize),
201 iewQueue(params->backComSize, params->forwardComSize),
202 activityRec(name(), NumStages,
203 params->backComSize + params->forwardComSize,
204 params->activity),

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213 } else {
214 _status = Idle;
215 }
216
217#if USE_CHECKER
218 if (params->checker) {
219 BaseCPU *temp_checker = params->checker;
220 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
221#if FULL_SYSTEM
222 checker->setSystem(params->system);
223#endif
224 } else {
225 checker = NULL;
226 }
227#endif // USE_CHECKER
228

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523 .prereq(miscRegfileWrites);
524}
525
526template <class Impl>
527Port *
528FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
529{
530 if (if_name == "dcache_port")
531 return iew.getDcachePort();
532 else if (if_name == "icache_port")
533 return fetch.getIcachePort();
534 else
535 panic("No Such Port\n");
536}
537
538template <class Impl>
539void
540FullO3CPU<Impl>::tick()
541{

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601{
602 BaseCPU::init();
603
604 // Set inSyscall so that the CPU doesn't squash when initially
605 // setting up registers.
606 for (ThreadID tid = 0; tid < numThreads; ++tid)
607 thread[tid]->inSyscall = true;
608
609#if FULL_SYSTEM
610 for (ThreadID tid = 0; tid < numThreads; tid++) {
611 ThreadContext *src_tc = threadContexts[tid];
612 TheISA::initCPU(src_tc, src_tc->contextId());
613 // Initialise the ThreadContext's memory proxies
614 thread[tid]->initMemProxies(thread[tid]->getTC());
615 }
616#endif

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1165 fetchQueue.advance();
1166 decodeQueue.advance();
1167 renameQueue.advance();
1168 iewQueue.advance();
1169 }
1170
1171 activityRec.reset();
1172
1173 BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort());
1174
1175 fetch.takeOverFrom();
1176 decode.takeOverFrom();
1177 rename.takeOverFrom();
1178 iew.takeOverFrom();
1179 commit.takeOverFrom();
1180
1181 assert(!tickEvent.scheduled() || tickEvent.squashed());

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