1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/the_isa.hh"
34#include "config/use_checker.hh"
35#include "cpu/activity.hh"
36#include "cpu/simple_thread.hh"
37#include "cpu/thread_context.hh"

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475 .precision(6);
476 totalIpc = totalCommittedInsts / numCycles;
477
478 this->fetch.regStats();
479 this->decode.regStats();
480 this->rename.regStats();
481 this->iew.regStats();
482 this->commit.regStats();
483}
484
485template <class Impl>
486Port *
487FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
488{
489 if (if_name == "dcache_port")
490 return iew.getDcachePort();

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1179{
1180 return this->isa[tid].readMiscRegNoEffect(misc_reg);
1181}
1182
1183template <class Impl>
1184TheISA::MiscReg
1185FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1186{
1187 return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1188}
1189
1190template <class Impl>
1191void
1192FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1193 const TheISA::MiscReg &val, ThreadID tid)
1194{
1195 this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1196}
1197
1198template <class Impl>
1199void
1200FullO3CPU<Impl>::setMiscReg(int misc_reg,
1201 const TheISA::MiscReg &val, ThreadID tid)
1202{
1203 this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1204}
1205
1206template <class Impl>
1207uint64_t
1208FullO3CPU<Impl>::readIntReg(int reg_idx)
1209{
1210 return regFile.readIntReg(reg_idx);
1211}
1212
1213template <class Impl>
1214FloatReg
1215FullO3CPU<Impl>::readFloatReg(int reg_idx)
1216{
1217 return regFile.readFloatReg(reg_idx);
1218}
1219
1220template <class Impl>
1221FloatRegBits
1222FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1223{
1224 return regFile.readFloatRegBits(reg_idx);
1225}
1226
1227template <class Impl>
1228void
1229FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1230{
1231 regFile.setIntReg(reg_idx, val);
1232}
1233
1234template <class Impl>
1235void
1236FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1237{
1238 regFile.setFloatReg(reg_idx, val);
1239}
1240
1241template <class Impl>
1242void
1243FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1244{
1245 regFile.setFloatRegBits(reg_idx, val);
1246}
1247
1248template <class Impl>
1249uint64_t
1250FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1251{
1252 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1253
1254 return regFile.readIntReg(phys_reg);
1255}
1256
1257template <class Impl>
1258float
1259FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1260{
1261 int idx = reg_idx + TheISA::NumIntRegs;
1262 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1263
1264 return regFile.readFloatReg(phys_reg);
1265}
1266
1267template <class Impl>
1268uint64_t
1269FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1270{
1271 int idx = reg_idx + TheISA::NumIntRegs;
1272 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1273
1274 return regFile.readFloatRegBits(phys_reg);
1275}
1276
1277template <class Impl>
1278void
1279FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1280{
1281 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1282
1283 regFile.setIntReg(phys_reg, val);
1284}
1285
1286template <class Impl>
1287void
1288FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1289{
1290 int idx = reg_idx + TheISA::NumIntRegs;
1291 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1292
1293 regFile.setFloatReg(phys_reg, val);
1294}
1295
1296template <class Impl>
1297void
1298FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1299{
1300 int idx = reg_idx + TheISA::NumIntRegs;
1301 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1302
1303 regFile.setFloatRegBits(phys_reg, val);
1304}
1305
1306template <class Impl>
1307TheISA::PCState

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1359void
1360FullO3CPU<Impl>::instDone(ThreadID tid)
1361{
1362 // Keep an instruction count.
1363 thread[tid]->numInst++;
1364 thread[tid]->numInsts++;
1365 committedInsts[tid]++;
1366 totalCommittedInsts++;
1367
1368 // Check for instruction-count-based events.
1369 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1370}
1371
1372template <class Impl>
1373void
1374FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
1375{
1376 removeInstsThisCycle = true;
1377

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