1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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112const char *
113FullO3CPU<Impl>::ActivateThreadEvent::description()
114{
115 return "FullO3CPU \"Activate Thread\" event";
116}
117
118template <class Impl>
119FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
120 : Event(&mainEventQueue, CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
121{
122}
123
124template <class Impl>
125void
126FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
127 FullO3CPU<Impl> *thread_cpu)
128{
129 tid = thread_num;
130 cpu = thread_cpu;
131 remove = false;
132}
133
134template <class Impl>
135void
136FullO3CPU<Impl>::DeallocateContextEvent::process()
137{
138 cpu->deactivateThread(tid);
139 if (remove)

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145FullO3CPU<Impl>::DeallocateContextEvent::description()
146{
147 return "FullO3CPU \"Deallocate Context\" event";
148}
149
150template <class Impl>
151FullO3CPU<Impl>::FullO3CPU(Params *params)
152 : BaseO3CPU(params),
153 tickEvent(this),
154 removeInstsThisCycle(false),
155 fetch(params),
156 decode(params),
157 rename(params),
158 iew(params),
159 commit(params),
160

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602
603template <class Impl>
604void
605FullO3CPU<Impl>::suspendContext(int tid)
606{
607 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
608 bool deallocated = deallocateContext(tid, false, 1);
609 // If this was the last thread then unschedule the tick event.
610 if (activeThreads.size() == 1 && !deallocated ||
611 activeThreads.size() == 0)
612 unscheduleTickEvent();
613 _status = Idle;
614}
615
616template <class Impl>
617void
618FullO3CPU<Impl>::haltContext(int tid)
619{

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652 }
653
654 //Copy Thread Data Into RegFile
655 //this->copyFromTC(tid);
656
657 //Set PC/NPC/NNPC
658 setPC(src_tc->readPC(), tid);
659 setNextPC(src_tc->readNextPC(), tid);
660#if ISA_HAS_DELAY_SLOT
661 setNextNPC(src_tc->readNextNPC(), tid);
662#endif
663
664 src_tc->setStatus(ThreadContext::Active);
665
666 activateContext(tid,1);
667
668 //Reset ROB/IQ/LSQ Entries
669 commit.rob->resetEntries();
670 iew.resetEntries();

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693 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
694
695 scoreboard.unsetReg(phys_reg);
696 freeList.addReg(phys_reg);
697 }
698
699 // Squash Throughout Pipeline
700 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
701 fetch.squash(0, squash_seq_num, true, tid);
702 decode.squash(tid);
703 rename.squash(squash_seq_num, tid);
704 iew.squash(tid);
705 commit.rob->squash(squash_seq_num, tid);
706
707 assert(iew.ldstQueue.getCount(tid) == 0);
708
709 // Reset ROB/IQ/LSQ Entries

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