1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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112const char *
113FullO3CPU<Impl>::ActivateThreadEvent::description()
114{
115 return "FullO3CPU \"Activate Thread\" event";
116}
117
118template <class Impl>
119FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
120 : Event(&mainEventQueue, CPU_Tick_Pri)
121{
122}
123
124template <class Impl>
125void
126FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
127 FullO3CPU *thread_cpu)
128{
129 tid = thread_num;
130 cpu = thread_cpu;
131}
132
133template <class Impl>
134void
135FullO3CPU<Impl>::DeallocateContextEvent::process()
136{
137 cpu->deactivateThread(tid);
138 if (remove)

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144FullO3CPU<Impl>::DeallocateContextEvent::description()
145{
146 return "FullO3CPU \"Deallocate Context\" event";
147}
148
149template <class Impl>
150FullO3CPU<Impl>::FullO3CPU(Params *params)
151 : BaseO3CPU(params),
152#if FULL_SYSTEM
153 itb(params->itb),
154 dtb(params->dtb),
155#endif
156 tickEvent(this),
157 removeInstsThisCycle(false),
158 fetch(params),
159 decode(params),
160 rename(params),
161 iew(params),
162 commit(params),
163

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605
606template <class Impl>
607void
608FullO3CPU<Impl>::suspendContext(int tid)
609{
610 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
611 bool deallocated = deallocateContext(tid, false, 1);
612 // If this was the last thread then unschedule the tick event.
613 if ((activeThreads.size() == 1 && !deallocated) || activeThreads.size() == 0)
614 unscheduleTickEvent();
615 _status = Idle;
616}
617
618template <class Impl>
619void
620FullO3CPU<Impl>::haltContext(int tid)
621{

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695 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
696
697 scoreboard.unsetReg(phys_reg);
698 freeList.addReg(phys_reg);
699 }
700
701 // Squash Throughout Pipeline
702 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
703 fetch.squash(0, sizeof(TheISA::MachInst), squash_seq_num, true, tid);
704 decode.squash(tid);
705 rename.squash(squash_seq_num, tid);
706 iew.squash(tid);
707 commit.rob->squash(squash_seq_num, tid);
708
709 assert(iew.ldstQueue.getCount(tid) == 0);
710
711 // Reset ROB/IQ/LSQ Entries

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