1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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845 return 0;
846 }
847}
848
849template <class Impl>
850void
851FullO3CPU<Impl>::resume()
852{
853#if FULL_SYSTEM
854 assert(system->getMemoryMode() == System::Timing);
855#endif
856 fetch.resume();
857 decode.resume();
858 rename.resume();
859 iew.resume();
860 commit.resume();
861
862 changeState(SimObject::Running);
863
864 if (_status == SwitchedOut || _status == Idle)
865 return;
866
867 if (!tickEvent.scheduled())
868 tickEvent.schedule(curTick);
869 _status = Running;
870}
871
872template <class Impl>
873void
874FullO3CPU<Impl>::signalDrained()

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