1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#if FULL_SYSTEM
36#include "sim/system.hh"
37#else
38#include "sim/process.hh"
39#endif
40
41#include "cpu/activity.hh"
42#include "cpu/simple_thread.hh"
43#include "cpu/thread_context.hh"

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788 thread[i]->getTC()->copyArchRegs(temp.getTC());
789 }
790}
791
792template <class Impl>
793unsigned int
794FullO3CPU<Impl>::drain(Event *drain_event)
795{
796 drainCount = 0;
797 fetch.drain();
798 decode.drain();
799 rename.drain();
800 iew.drain();
801 commit.drain();
802
803 // Wake the CPU and record activity so everything can drain out if

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858}
859
860template <class Impl>
861void
862FullO3CPU<Impl>::switchOut()
863{
864 fetch.switchOut();
865 rename.switchOut();
866 commit.switchOut();
867 instList.clear();
868 while (!removeList.empty()) {
869 removeList.pop();
870 }
871
872 _status = SwitchedOut;
873#if USE_CHECKER

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926 tickEvent.schedule(curTick);
927 }
928 }
929 if (!tickEvent.scheduled())
930 tickEvent.schedule(curTick);
931}
932
933template <class Impl>
934uint64_t
935FullO3CPU<Impl>::readIntReg(int reg_idx)
936{
937 return regFile.readIntReg(reg_idx);
938}
939
940template <class Impl>
941FloatReg

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