1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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707*/
708}
709
710template <class Impl>
711bool
712FullO3CPU<Impl>::drain(Event *drain_event)
713{
714 drainCount = 0;
715 drainEvent = drain_event;
716 fetch.drain();
717 decode.drain();
718 rename.drain();
719 iew.drain();
720 commit.drain();
721
722 // Wake the CPU and record activity so everything can drain out if
723 // the CPU is currently idle.
724 wakeCPU();
725 activityRec.activity();
726
727 return false;
728}
729
730template <class Impl>
731void
732FullO3CPU<Impl>::resume()
733{
734 if (_status == SwitchedOut)
735 return;

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746
747template <class Impl>
748void
749FullO3CPU<Impl>::signalDrained()
750{
751 if (++drainCount == NumStages) {
752 if (tickEvent.scheduled())
753 tickEvent.squash();
754 _status = Drained;
755 drainEvent->process();
756 }
757 assert(drainCount <= 5);
758}
759
760template <class Impl>
761void
762FullO3CPU<Impl>::switchOut()
763{

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