1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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153
154 globalSeqNum(1),
155
156#if FULL_SYSTEM
157 system(params->system),
158 physmem(system->physmem),
159#endif // FULL_SYSTEM
160 mem(params->mem),
161 switchCount(0),
162 deferRegistration(params->deferRegistration),
163 numThreads(number_of_threads)
164{
165 _status = Idle;
166
167 checker = NULL;
168
169 if (params->checker) {

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703 activeThreads.erase(isActive);
704
705 removeThread(tid);
706 }
707*/
708}
709
710template <class Impl>
711void
712FullO3CPU<Impl>::switchOut()
713{
714 switchCount = 0;
715 fetch.switchOut();
716 decode.switchOut();
717 rename.switchOut();
718 iew.switchOut();
719 commit.switchOut();
720
721 // Wake the CPU and record activity so everything can drain out if
722 // the CPU is currently idle.
723 wakeCPU();
724 activityRec.activity();
725}
726
727template <class Impl>
728void
729FullO3CPU<Impl>::signalSwitched()
730{
731 if (++switchCount == NumStages) {
732 fetch.doSwitchOut();
733 rename.doSwitchOut();
734 commit.doSwitchOut();
735 instList.clear();
736 while (!removeList.empty()) {
737 removeList.pop();
738 }
739
740#if USE_CHECKER
741 if (checker)
742 checker->switchOut();
743#endif
744
745 if (tickEvent.scheduled())
746 tickEvent.squash();
747 _status = SwitchedOut;
748 }
749 assert(switchCount <= 5);
750}
751
752template <class Impl>
753void
754FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
755{
756 // Flush out any old data from the time buffers.
757 for (int i = 0; i < 10; ++i) {
758 timeBuffer.advance();
759 fetchQueue.advance();
760 decodeQueue.advance();
761 renameQueue.advance();

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