1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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153
154 globalSeqNum(1),
155
156#if FULL_SYSTEM
157 system(params->system),
158 physmem(system->physmem),
159#endif // FULL_SYSTEM
160 mem(params->mem),
161 switchCount(0),
162 deferRegistration(params->deferRegistration),
163 numThreads(number_of_threads)
164{
165 _status = Idle;
166
167 checker = NULL;
168
169 if (params->checker) {

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708 activeThreads.erase(isActive);
709
710 removeThread(tid);
711 }
712*/
713}
714
715template <class Impl>
716void
717FullO3CPU<Impl>::switchOut()
718{
719 switchCount = 0;
720 fetch.switchOut();
721 decode.switchOut();
722 rename.switchOut();
723 iew.switchOut();
724 commit.switchOut();
725
726 // Wake the CPU and record activity so everything can drain out if
727 // the CPU is currently idle.
728 wakeCPU();
729 activityRec.activity();
730}
731
732template <class Impl>
733void
734FullO3CPU<Impl>::signalSwitched()
735{
736 if (++switchCount == NumStages) {
737 fetch.doSwitchOut();
738 rename.doSwitchOut();
739 commit.doSwitchOut();
740 instList.clear();
741 while (!removeList.empty()) {
742 removeList.pop();
743 }
744
745#if USE_CHECKER
746 if (checker)
747 checker->switchOut();
748#endif
749
750 if (tickEvent.scheduled())
751 tickEvent.squash();
752 _status = SwitchedOut;
753 }
754 assert(switchCount <= 5);
755}
756
757template <class Impl>
758void
759FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
760{
761 // Flush out any old data from the time buffers.
762 for (int i = 0; i < 10; ++i) {
763 timeBuffer.advance();
764 fetchQueue.advance();
765 decodeQueue.advance();
766 renameQueue.advance();

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