1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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81template <class Impl>
82const char *
83FullO3CPU<Impl>::TickEvent::description()
84{
85 return "FullO3CPU tick event";
86}
87
88template <class Impl>
89FullO3CPU<Impl>::FullO3CPU(Params *params)
90 : BaseO3CPU(params),
91 tickEvent(this),
92 removeInstsThisCycle(false),
93 fetch(params),
94 decode(params),
95 rename(params),
96 iew(params),

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252 }
253 rename.setFreeList(&freeList);
254
255 // Setup the ROB for whichever stages need it.
256 commit.setROB(&rob);
257
258 lastRunningCycle = curTick;
259
260 contextSwitch = false;
261}
262
263template <class Impl>
264FullO3CPU<Impl>::~FullO3CPU()
265{
266}
267

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569
570 //do waitlist
571 cpuWaitList.push_back(tid);
572 }
573}
574
575template <class Impl>
576void
577FullO3CPU<Impl>::activateContext(int tid, int delay)
578{
579 // Needs to set each stage to running as well.
580 list<unsigned>::iterator isActive = find(
581 activeThreads.begin(), activeThreads.end(), tid);
582
583 if (isActive == activeThreads.end()) {
584 //May Need to Re-code this if the delay variable is the
585 //delay needed for thread to activate
586 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
587 tid);
588
589 activeThreads.push_back(tid);
590 }
591
592 assert(_status == Idle || _status == SwitchedOut);
593
594 scheduleTickEvent(delay);
595
596 // Be sure to signal that there's some activity so the CPU doesn't
597 // deschedule itself.
598 activityRec.activity();
599 fetch.wakeFromQuiesce();
600
601 _status = Running;
602}
603
604template <class Impl>
605void
606FullO3CPU<Impl>::suspendContext(int tid)
607{
608 DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid);
609 unscheduleTickEvent();

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