1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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920template <class Impl>
921Fault
922FullO3CPU<Impl>::hwrei(ThreadID tid)
923{
924#if THE_ISA == ALPHA_ISA
925 // Need to clear the lock flag upon returning from an interrupt.
926 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
927
928 this->thread[tid]->kernelStats->hwrei();
929
930 // FIXME: XXX check for interrupts? XXX
931#endif
932 return NoFault;
933}
934
935template <class Impl>
936bool
937FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
938{
939#if THE_ISA == ALPHA_ISA
940 if (this->thread[tid]->kernelStats)
941 this->thread[tid]->kernelStats->callpal(palFunc,
942 this->threadContexts[tid]);
943
944 switch (palFunc) {
945 case PAL::halt:
946 halt();
947 if (--System::numSystemsRunning == 0)
948 exitSimLoop("all cpus halted");
949 break;
950

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