1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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154 commit(this, params),
155
156 /* It is mandatory that all SMT threads use the same renaming mode as
157 * they are sharing registers and rename */
158 vecMode(RenameMode<TheISA::ISA>::init(params->isa[0])),
159 regFile(params->numPhysIntRegs,
160 params->numPhysFloatRegs,
161 params->numPhysVecRegs,
162 params->numPhysCCRegs,
163 vecMode),
164
165 freeList(name() + ".freelist", &regFile),
166
167 rob(this, params),
168
169 scoreboard(name() + ".scoreboard",

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253 "or edit your workload size.");
254 }
255 }
256
257 //Make Sure That this a Valid Architeture
258 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
259 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
260 assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
261 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
262
263 rename.setScoreboard(&scoreboard);
264 iew.setScoreboard(&scoreboard);
265
266 // Setup the rename map for whichever stages need it.
267 for (ThreadID tid = 0; tid < numThreads; tid++) {
268 isa[tid] = params->isa[tid];

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320 RegId lrid = RegId(VecElemClass, ridx, ldx);
321 PhysRegIdPtr phys_elem = freeList.getVecElem();
322 renameMap[tid].setEntry(lrid, phys_elem);
323 commitRenameMap[tid].setEntry(lrid, phys_elem);
324 }
325 }
326 }
327
328 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
329 PhysRegIdPtr phys_reg = freeList.getCCReg();
330 renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
331 commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
332 }
333 }
334
335 rename.setRenameMap(renameMap);

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533 .desc("number of vector regfile reads")
534 .prereq(vecRegfileReads);
535
536 vecRegfileWrites
537 .name(name() + ".vec_regfile_writes")
538 .desc("number of vector regfile writes")
539 .prereq(vecRegfileWrites);
540
541 ccRegfileReads
542 .name(name() + ".cc_regfile_reads")
543 .desc("number of cc regfile reads")
544 .prereq(ccRegfileReads);
545
546 ccRegfileWrites
547 .name(name() + ".cc_regfile_writes")
548 .desc("number of cc regfile writes")

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878 // Unbind Float Regs from Rename Map
879 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
880 reg_id.index()++) {
881 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
882 scoreboard.unsetReg(phys_reg);
883 freeList.addReg(phys_reg);
884 }
885
886 // Unbind condition-code Regs from Rename Map
887 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
888 reg_id.index()++) {
889 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
890 scoreboard.unsetReg(phys_reg);
891 freeList.addReg(phys_reg);
892 }
893

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1329auto
1330FullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem&
1331{
1332 vecRegfileReads++;
1333 return regFile.readVecElem(phys_reg);
1334}
1335
1336template <class Impl>
1337CCReg
1338FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1339{
1340 ccRegfileReads++;
1341 return regFile.readCCReg(phys_reg);
1342}
1343
1344template <class Impl>

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1370FullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val)
1371{
1372 vecRegfileWrites++;
1373 regFile.setVecElem(phys_reg, val);
1374}
1375
1376template <class Impl>
1377void
1378FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1379{
1380 ccRegfileWrites++;
1381 regFile.setCCReg(phys_reg, val);
1382}
1383
1384template <class Impl>
1385RegVal

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1429 ThreadID tid) const -> const VecElem&
1430{
1431 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1432 RegId(VecElemClass, reg_idx, ldx));
1433 return readVecElem(phys_reg);
1434}
1435
1436template <class Impl>
1437CCReg
1438FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1439{
1440 ccRegfileReads++;
1441 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1442 RegId(CCRegClass, reg_idx));
1443
1444 return regFile.readCCReg(phys_reg);

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1483{
1484 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1485 RegId(VecElemClass, reg_idx, ldx));
1486 setVecElem(phys_reg, val);
1487}
1488
1489template <class Impl>
1490void
1491FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1492{
1493 ccRegfileWrites++;
1494 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1495 RegId(CCRegClass, reg_idx));
1496
1497 regFile.setCCReg(phys_reg, val);
1498}

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