1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#include "cpu/o3/cpu.hh"
48
49#include "arch/kernel_stats.hh"
50#include "config/the_isa.hh"
51#include "cpu/activity.hh"
52#include "cpu/checker/cpu.hh"
53#include "cpu/checker/thread_context.hh"
54#include "cpu/o3/isa_specific.hh"
55#include "cpu/o3/thread_context.hh"
56#include "cpu/quiesce_event.hh"
57#include "cpu/simple_thread.hh"
58#include "cpu/thread_context.hh"
59#include "debug/Activity.hh"
60#include "debug/Drain.hh"
61#include "debug/O3CPU.hh"
62#include "debug/Quiesce.hh"
63#include "enums/MemoryMode.hh"
64#include "sim/core.hh"
65#include "sim/full_system.hh"
66#include "sim/process.hh"
67#include "sim/stat_control.hh"
68#include "sim/system.hh"
69
70#if THE_ISA == ALPHA_ISA
71#include "arch/alpha/osfpal.hh"
72#include "debug/Activity.hh"
73
74#endif
75
76struct BaseCPUParams;
77
78using namespace TheISA;
79using namespace std;
80
81BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
82 : BaseCPU(params)
83{
84}
85
86void
87BaseO3CPU::regStats()
88{
89 BaseCPU::regStats();
90}
91
92template<class Impl>
93bool
94FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
95{
96 DPRINTF(O3CPU, "Fetch unit received timing\n");
97 // We shouldn't ever get a cacheable block in Modified state
98 assert(pkt->req->isUncacheable() ||
99 !(pkt->cacheResponding() && !pkt->hasSharers()));
100 fetch->processCacheCompletion(pkt);
101
102 return true;
103}
104
105template<class Impl>
106void
107FullO3CPU<Impl>::IcachePort::recvReqRetry()
108{
109 fetch->recvReqRetry();
110}
111
112template <class Impl>
113bool
114FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
115{
116 return lsq->recvTimingResp(pkt);
117}
118
119template <class Impl>
120void
121FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
122{
123 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
124 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
125 cpu->wakeup(tid);
126 }
127 }
128 lsq->recvTimingSnoopReq(pkt);
129}
130
131template <class Impl>
132void
133FullO3CPU<Impl>::DcachePort::recvReqRetry()
134{
135 lsq->recvReqRetry();
136}
137
138template <class Impl>
139FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
140 : Event(CPU_Tick_Pri), cpu(c)
141{
142}
143
144template <class Impl>
145void
146FullO3CPU<Impl>::TickEvent::process()
147{
148 cpu->tick();
149}
150
151template <class Impl>
152const char *
153FullO3CPU<Impl>::TickEvent::description() const
154{
155 return "FullO3CPU tick";
156}
157
158template <class Impl>
159FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
160 : BaseO3CPU(params),
161 itb(params->itb),
162 dtb(params->dtb),
163 tickEvent(this),
164#ifndef NDEBUG
165 instcount(0),
166#endif
167 removeInstsThisCycle(false),
168 fetch(this, params),
169 decode(this, params),
170 rename(this, params),
171 iew(this, params),
172 commit(this, params),
173
174 regFile(params->numPhysIntRegs,
175 params->numPhysFloatRegs,
176 params->numPhysCCRegs),
177
178 freeList(name() + ".freelist", ®File),
179
180 rob(this, params),
181
182 scoreboard(name() + ".scoreboard",
183 regFile.totalNumPhysRegs()),
184
185 isa(numThreads, NULL),
186
187 icachePort(&fetch, this),
188 dcachePort(&iew.ldstQueue, this),
189
190 timeBuffer(params->backComSize, params->forwardComSize),
191 fetchQueue(params->backComSize, params->forwardComSize),
192 decodeQueue(params->backComSize, params->forwardComSize),
193 renameQueue(params->backComSize, params->forwardComSize),
194 iewQueue(params->backComSize, params->forwardComSize),
195 activityRec(name(), NumStages,
196 params->backComSize + params->forwardComSize,
197 params->activity),
198
199 globalSeqNum(1),
200 system(params->system),
201 lastRunningCycle(curCycle())
202{
203 if (!params->switched_out) {
204 _status = Running;
205 } else {
206 _status = SwitchedOut;
207 }
208
209 if (params->checker) {
210 BaseCPU *temp_checker = params->checker;
211 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
212 checker->setIcachePort(&icachePort);
213 checker->setSystem(params->system);
214 } else {
215 checker = NULL;
216 }
217
218 if (!FullSystem) {
219 thread.resize(numThreads);
220 tids.resize(numThreads);
221 }
222
223 // The stages also need their CPU pointer setup. However this
224 // must be done at the upper level CPU because they have pointers
225 // to the upper level CPU, and not this FullO3CPU.
226
227 // Set up Pointers to the activeThreads list for each stage
228 fetch.setActiveThreads(&activeThreads);
229 decode.setActiveThreads(&activeThreads);
230 rename.setActiveThreads(&activeThreads);
231 iew.setActiveThreads(&activeThreads);
232 commit.setActiveThreads(&activeThreads);
233
234 // Give each of the stages the time buffer they will use.
235 fetch.setTimeBuffer(&timeBuffer);
236 decode.setTimeBuffer(&timeBuffer);
237 rename.setTimeBuffer(&timeBuffer);
238 iew.setTimeBuffer(&timeBuffer);
239 commit.setTimeBuffer(&timeBuffer);
240
241 // Also setup each of the stages' queues.
242 fetch.setFetchQueue(&fetchQueue);
243 decode.setFetchQueue(&fetchQueue);
244 commit.setFetchQueue(&fetchQueue);
245 decode.setDecodeQueue(&decodeQueue);
246 rename.setDecodeQueue(&decodeQueue);
247 rename.setRenameQueue(&renameQueue);
248 iew.setRenameQueue(&renameQueue);
249 iew.setIEWQueue(&iewQueue);
250 commit.setIEWQueue(&iewQueue);
251 commit.setRenameQueue(&renameQueue);
252
253 commit.setIEWStage(&iew);
254 rename.setIEWStage(&iew);
255 rename.setCommitStage(&commit);
256
257 ThreadID active_threads;
258 if (FullSystem) {
259 active_threads = 1;
260 } else {
261 active_threads = params->workload.size();
262
263 if (active_threads > Impl::MaxThreads) {
264 panic("Workload Size too large. Increase the 'MaxThreads' "
265 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
266 "or edit your workload size.");
267 }
268 }
269
270 //Make Sure That this a Valid Architeture
271 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
272 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
273 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
274
275 rename.setScoreboard(&scoreboard);
276 iew.setScoreboard(&scoreboard);
277
278 // Setup the rename map for whichever stages need it.
279 for (ThreadID tid = 0; tid < numThreads; tid++) {
280 isa[tid] = params->isa[tid];
281
282 // Only Alpha has an FP zero register, so for other ISAs we
283 // use an invalid FP register index to avoid special treatment
284 // of any valid FP reg.
285 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
286 RegIndex fpZeroReg =
287 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
288
289 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
290 &freeList);
291
292 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
293 &freeList);
294 }
295
296 // Initialize rename map to assign physical registers to the
297 // architectural registers for active threads only.
298 for (ThreadID tid = 0; tid < active_threads; tid++) {
299 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
300 // Note that we can't use the rename() method because we don't
301 // want special treatment for the zero register at this point
302 PhysRegIdPtr phys_reg = freeList.getIntReg();
303 renameMap[tid].setIntEntry(ridx, phys_reg);
304 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
305 }
306
307 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
308 PhysRegIdPtr phys_reg = freeList.getFloatReg();
309 renameMap[tid].setFloatEntry(ridx, phys_reg);
310 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
311 }
312
313 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
314 PhysRegIdPtr phys_reg = freeList.getCCReg();
315 renameMap[tid].setCCEntry(ridx, phys_reg);
316 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
317 }
318 }
319
320 rename.setRenameMap(renameMap);
321 commit.setRenameMap(commitRenameMap);
322 rename.setFreeList(&freeList);
323
324 // Setup the ROB for whichever stages need it.
325 commit.setROB(&rob);
326
327 lastActivatedCycle = 0;
328#if 0
329 // Give renameMap & rename stage access to the freeList;
330 for (ThreadID tid = 0; tid < numThreads; tid++)
331 globalSeqNum[tid] = 1;
332#endif
333
334 DPRINTF(O3CPU, "Creating O3CPU object.\n");
335
336 // Setup any thread state.
337 this->thread.resize(this->numThreads);
338
339 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
340 if (FullSystem) {
341 // SMT is not supported in FS mode yet.
342 assert(this->numThreads == 1);
343 this->thread[tid] = new Thread(this, 0, NULL);
344 } else {
345 if (tid < params->workload.size()) {
346 DPRINTF(O3CPU, "Workload[%i] process is %#x",
347 tid, this->thread[tid]);
348 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
349 (typename Impl::O3CPU *)(this),
350 tid, params->workload[tid]);
351
352 //usedTids[tid] = true;
353 //threadMap[tid] = tid;
354 } else {
355 //Allocate Empty thread so M5 can use later
356 //when scheduling threads to CPU
357 Process* dummy_proc = NULL;
358
359 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
360 (typename Impl::O3CPU *)(this),
361 tid, dummy_proc);
362 //usedTids[tid] = false;
363 }
364 }
365
366 ThreadContext *tc;
367
368 // Setup the TC that will serve as the interface to the threads/CPU.
369 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
370
371 tc = o3_tc;
372
373 // If we're using a checker, then the TC should be the
374 // CheckerThreadContext.
375 if (params->checker) {
376 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
377 o3_tc, this->checker);
378 }
379
380 o3_tc->cpu = (typename Impl::O3CPU *)(this);
381 assert(o3_tc->cpu);
382 o3_tc->thread = this->thread[tid];
383
384 // Setup quiesce event.
385 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
386
387 // Give the thread the TC.
388 this->thread[tid]->tc = tc;
389
390 // Add the TC to the CPU's list of TC's.
391 this->threadContexts.push_back(tc);
392 }
393
394 // FullO3CPU always requires an interrupt controller.
395 if (!params->switched_out && interrupts.empty()) {
396 fatal("FullO3CPU %s has no interrupt controller.\n"
397 "Ensure createInterruptController() is called.\n", name());
398 }
399
400 for (ThreadID tid = 0; tid < this->numThreads; tid++)
401 this->thread[tid]->setFuncExeInst(0);
402}
403
404template <class Impl>
405FullO3CPU<Impl>::~FullO3CPU()
406{
407}
408
409template <class Impl>
410void
411FullO3CPU<Impl>::regProbePoints()
412{
413 BaseCPU::regProbePoints();
414
415 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
416 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
417
418 fetch.regProbePoints();
419 rename.regProbePoints();
420 iew.regProbePoints();
421 commit.regProbePoints();
422}
423
424template <class Impl>
425void
426FullO3CPU<Impl>::regStats()
427{
428 BaseO3CPU::regStats();
429
430 // Register any of the O3CPU's stats here.
431 timesIdled
432 .name(name() + ".timesIdled")
433 .desc("Number of times that the entire CPU went into an idle state and"
434 " unscheduled itself")
435 .prereq(timesIdled);
436
437 idleCycles
438 .name(name() + ".idleCycles")
439 .desc("Total number of cycles that the CPU has spent unscheduled due "
440 "to idling")
441 .prereq(idleCycles);
442
443 quiesceCycles
444 .name(name() + ".quiesceCycles")
445 .desc("Total number of cycles that CPU has spent quiesced or waiting "
446 "for an interrupt")
447 .prereq(quiesceCycles);
448
449 // Number of Instructions simulated
450 // --------------------------------
451 // Should probably be in Base CPU but need templated
452 // MaxThreads so put in here instead
453 committedInsts
454 .init(numThreads)
455 .name(name() + ".committedInsts")
456 .desc("Number of Instructions Simulated")
457 .flags(Stats::total);
458
459 committedOps
460 .init(numThreads)
461 .name(name() + ".committedOps")
462 .desc("Number of Ops (including micro ops) Simulated")
463 .flags(Stats::total);
464
465 cpi
466 .name(name() + ".cpi")
467 .desc("CPI: Cycles Per Instruction")
468 .precision(6);
469 cpi = numCycles / committedInsts;
470
471 totalCpi
472 .name(name() + ".cpi_total")
473 .desc("CPI: Total CPI of All Threads")
474 .precision(6);
475 totalCpi = numCycles / sum(committedInsts);
476
477 ipc
478 .name(name() + ".ipc")
479 .desc("IPC: Instructions Per Cycle")
480 .precision(6);
481 ipc = committedInsts / numCycles;
482
483 totalIpc
484 .name(name() + ".ipc_total")
485 .desc("IPC: Total IPC of All Threads")
486 .precision(6);
487 totalIpc = sum(committedInsts) / numCycles;
488
489 this->fetch.regStats();
490 this->decode.regStats();
491 this->rename.regStats();
492 this->iew.regStats();
493 this->commit.regStats();
494 this->rob.regStats();
495
496 intRegfileReads
497 .name(name() + ".int_regfile_reads")
498 .desc("number of integer regfile reads")
499 .prereq(intRegfileReads);
500
501 intRegfileWrites
502 .name(name() + ".int_regfile_writes")
503 .desc("number of integer regfile writes")
504 .prereq(intRegfileWrites);
505
506 fpRegfileReads
507 .name(name() + ".fp_regfile_reads")
508 .desc("number of floating regfile reads")
509 .prereq(fpRegfileReads);
510
511 fpRegfileWrites
512 .name(name() + ".fp_regfile_writes")
513 .desc("number of floating regfile writes")
514 .prereq(fpRegfileWrites);
515
516 ccRegfileReads
517 .name(name() + ".cc_regfile_reads")
518 .desc("number of cc regfile reads")
519 .prereq(ccRegfileReads);
520
521 ccRegfileWrites
522 .name(name() + ".cc_regfile_writes")
523 .desc("number of cc regfile writes")
524 .prereq(ccRegfileWrites);
525
526 miscRegfileReads
527 .name(name() + ".misc_regfile_reads")
528 .desc("number of misc regfile reads")
529 .prereq(miscRegfileReads);
530
531 miscRegfileWrites
532 .name(name() + ".misc_regfile_writes")
533 .desc("number of misc regfile writes")
534 .prereq(miscRegfileWrites);
535}
536
537template <class Impl>
538void
539FullO3CPU<Impl>::tick()
540{
541 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
542 assert(!switchedOut());
543 assert(drainState() != DrainState::Drained);
544
545 ++numCycles;
546 ppCycles->notify(1);
547
548// activity = false;
549
550 //Tick each of the stages
551 fetch.tick();
552
553 decode.tick();
554
555 rename.tick();
556
557 iew.tick();
558
559 commit.tick();
560
561 // Now advance the time buffers
562 timeBuffer.advance();
563
564 fetchQueue.advance();
565 decodeQueue.advance();
566 renameQueue.advance();
567 iewQueue.advance();
568
569 activityRec.advance();
570
571 if (removeInstsThisCycle) {
572 cleanUpRemovedInsts();
573 }
574
575 if (!tickEvent.scheduled()) {
576 if (_status == SwitchedOut) {
577 DPRINTF(O3CPU, "Switched out!\n");
578 // increment stat
579 lastRunningCycle = curCycle();
580 } else if (!activityRec.active() || _status == Idle) {
581 DPRINTF(O3CPU, "Idle!\n");
582 lastRunningCycle = curCycle();
583 timesIdled++;
584 } else {
585 schedule(tickEvent, clockEdge(Cycles(1)));
586 DPRINTF(O3CPU, "Scheduling next tick!\n");
587 }
588 }
589
590 if (!FullSystem)
591 updateThreadPriority();
592
593 tryDrain();
594}
595
596template <class Impl>
597void
598FullO3CPU<Impl>::init()
599{
600 BaseCPU::init();
601
602 for (ThreadID tid = 0; tid < numThreads; ++tid) {
603 // Set noSquashFromTC so that the CPU doesn't squash when initially
604 // setting up registers.
605 thread[tid]->noSquashFromTC = true;
606 // Initialise the ThreadContext's memory proxies
607 thread[tid]->initMemProxies(thread[tid]->getTC());
608 }
609
610 if (FullSystem && !params()->switched_out) {
611 for (ThreadID tid = 0; tid < numThreads; tid++) {
612 ThreadContext *src_tc = threadContexts[tid];
613 TheISA::initCPU(src_tc, src_tc->contextId());
614 }
615 }
616
617 // Clear noSquashFromTC.
618 for (int tid = 0; tid < numThreads; ++tid)
619 thread[tid]->noSquashFromTC = false;
620
621 commit.setThreads(thread);
622}
623
624template <class Impl>
625void
626FullO3CPU<Impl>::startup()
627{
628 BaseCPU::startup();
629 for (int tid = 0; tid < numThreads; ++tid)
630 isa[tid]->startup(threadContexts[tid]);
631
632 fetch.startupStage();
633 decode.startupStage();
634 iew.startupStage();
635 rename.startupStage();
636 commit.startupStage();
637}
638
639template <class Impl>
640void
641FullO3CPU<Impl>::activateThread(ThreadID tid)
642{
643 list<ThreadID>::iterator isActive =
644 std::find(activeThreads.begin(), activeThreads.end(), tid);
645
646 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
647 assert(!switchedOut());
648
649 if (isActive == activeThreads.end()) {
650 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
651 tid);
652
653 activeThreads.push_back(tid);
654 }
655}
656
657template <class Impl>
658void
659FullO3CPU<Impl>::deactivateThread(ThreadID tid)
660{
661 //Remove From Active List, if Active
662 list<ThreadID>::iterator thread_it =
663 std::find(activeThreads.begin(), activeThreads.end(), tid);
664
665 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
666 assert(!switchedOut());
667
668 if (thread_it != activeThreads.end()) {
669 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
670 tid);
671 activeThreads.erase(thread_it);
672 }
673
674 fetch.deactivateThread(tid);
675 commit.deactivateThread(tid);
676}
677
678template <class Impl>
679Counter
680FullO3CPU<Impl>::totalInsts() const
681{
682 Counter total(0);
683
684 ThreadID size = thread.size();
685 for (ThreadID i = 0; i < size; i++)
686 total += thread[i]->numInst;
687
688 return total;
689}
690
691template <class Impl>
692Counter
693FullO3CPU<Impl>::totalOps() const
694{
695 Counter total(0);
696
697 ThreadID size = thread.size();
698 for (ThreadID i = 0; i < size; i++)
699 total += thread[i]->numOp;
700
701 return total;
702}
703
704template <class Impl>
705void
706FullO3CPU<Impl>::activateContext(ThreadID tid)
707{
708 assert(!switchedOut());
709
710 // Needs to set each stage to running as well.
711 activateThread(tid);
712
713 // We don't want to wake the CPU if it is drained. In that case,
714 // we just want to flag the thread as active and schedule the tick
715 // event from drainResume() instead.
716 if (drainState() == DrainState::Drained)
717 return;
718
719 // If we are time 0 or if the last activation time is in the past,
720 // schedule the next tick and wake up the fetch unit
721 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
722 scheduleTickEvent(Cycles(0));
723
724 // Be sure to signal that there's some activity so the CPU doesn't
725 // deschedule itself.
726 activityRec.activity();
727 fetch.wakeFromQuiesce();
728
729 Cycles cycles(curCycle() - lastRunningCycle);
730 // @todo: This is an oddity that is only here to match the stats
731 if (cycles != 0)
732 --cycles;
733 quiesceCycles += cycles;
734
735 lastActivatedCycle = curTick();
736
737 _status = Running;
738
739 BaseCPU::activateContext(tid);
740 }
741}
742
743template <class Impl>
744void
745FullO3CPU<Impl>::suspendContext(ThreadID tid)
746{
747 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
748 assert(!switchedOut());
749
750 deactivateThread(tid);
751
752 // If this was the last thread then unschedule the tick event.
753 if (activeThreads.size() == 0) {
754 unscheduleTickEvent();
755 lastRunningCycle = curCycle();
756 _status = Idle;
757 }
758
759 DPRINTF(Quiesce, "Suspending Context\n");
760
761 BaseCPU::suspendContext(tid);
762}
763
764template <class Impl>
765void
766FullO3CPU<Impl>::haltContext(ThreadID tid)
767{
768 //For now, this is the same as deallocate
769 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
770 assert(!switchedOut());
771
772 deactivateThread(tid);
773 removeThread(tid);
774}
775
776template <class Impl>
777void
778FullO3CPU<Impl>::insertThread(ThreadID tid)
779{
780 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
781 // Will change now that the PC and thread state is internal to the CPU
782 // and not in the ThreadContext.
783 ThreadContext *src_tc;
784 if (FullSystem)
785 src_tc = system->threadContexts[tid];
786 else
787 src_tc = tcBase(tid);
788
789 //Bind Int Regs to Rename Map
790
791 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
792 reg_id.regIdx++) {
793 PhysRegIdPtr phys_reg = freeList.getIntReg();
794 renameMap[tid].setEntry(reg_id, phys_reg);
795 scoreboard.setReg(phys_reg);
796 }
797
798 //Bind Float Regs to Rename Map
799 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
800 reg_id.regIdx++) {
801 PhysRegIdPtr phys_reg = freeList.getFloatReg();
802 renameMap[tid].setEntry(reg_id, phys_reg);
803 scoreboard.setReg(phys_reg);
804 }
805
806 //Bind condition-code Regs to Rename Map
807 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
808 reg_id.regIdx++) {
809 PhysRegIdPtr phys_reg = freeList.getCCReg();
810 renameMap[tid].setEntry(reg_id, phys_reg);
811 scoreboard.setReg(phys_reg);
812 }
813
814 //Copy Thread Data Into RegFile
815 //this->copyFromTC(tid);
816
817 //Set PC/NPC/NNPC
818 pcState(src_tc->pcState(), tid);
819
820 src_tc->setStatus(ThreadContext::Active);
821
822 activateContext(tid);
823
824 //Reset ROB/IQ/LSQ Entries
825 commit.rob->resetEntries();
826 iew.resetEntries();
827}
828
829template <class Impl>
830void
831FullO3CPU<Impl>::removeThread(ThreadID tid)
832{
833 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
834
835 // Copy Thread Data From RegFile
836 // If thread is suspended, it might be re-allocated
837 // this->copyToTC(tid);
838
839
840 // @todo: 2-27-2008: Fix how we free up rename mappings
841 // here to alleviate the case for double-freeing registers
842 // in SMT workloads.
843
844 // Unbind Int Regs from Rename Map
845 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
846 reg_id.regIdx++) {
847 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
848 scoreboard.unsetReg(phys_reg);
849 freeList.addReg(phys_reg);
850 }
851
852 // Unbind Float Regs from Rename Map
853 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
854 reg_id.regIdx++) {
855 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
856 scoreboard.unsetReg(phys_reg);
857 freeList.addReg(phys_reg);
858 }
859
860 // Unbind condition-code Regs from Rename Map
861 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
862 reg_id.regIdx++) {
863 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
864 scoreboard.unsetReg(phys_reg);
865 freeList.addReg(phys_reg);
866 }
867
868 // Squash Throughout Pipeline
869 DynInstPtr inst = commit.rob->readHeadInst(tid);
870 InstSeqNum squash_seq_num = inst->seqNum;
871 fetch.squash(0, squash_seq_num, inst, tid);
872 decode.squash(tid);
873 rename.squash(squash_seq_num, tid);
874 iew.squash(tid);
875 iew.ldstQueue.squash(squash_seq_num, tid);
876 commit.rob->squash(squash_seq_num, tid);
877
878
879 assert(iew.instQueue.getCount(tid) == 0);
880 assert(iew.ldstQueue.getCount(tid) == 0);
881
882 // Reset ROB/IQ/LSQ Entries
883
884 // Commented out for now. This should be possible to do by
885 // telling all the pipeline stages to drain first, and then
886 // checking until the drain completes. Once the pipeline is
887 // drained, call resetEntries(). - 10-09-06 ktlim
888/*
889 if (activeThreads.size() >= 1) {
890 commit.rob->resetEntries();
891 iew.resetEntries();
892 }
893*/
894}
895
896template <class Impl>
897Fault
898FullO3CPU<Impl>::hwrei(ThreadID tid)
899{
900#if THE_ISA == ALPHA_ISA
901 // Need to clear the lock flag upon returning from an interrupt.
902 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
903
904 this->thread[tid]->kernelStats->hwrei();
905
906 // FIXME: XXX check for interrupts? XXX
907#endif
908 return NoFault;
909}
910
911template <class Impl>
912bool
913FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
914{
915#if THE_ISA == ALPHA_ISA
916 if (this->thread[tid]->kernelStats)
917 this->thread[tid]->kernelStats->callpal(palFunc,
918 this->threadContexts[tid]);
919
920 switch (palFunc) {
921 case PAL::halt:
922 halt();
923 if (--System::numSystemsRunning == 0)
924 exitSimLoop("all cpus halted");
925 break;
926
927 case PAL::bpt:
928 case PAL::bugchk:
929 if (this->system->breakpoint())
930 return false;
931 break;
932 }
933#endif
934 return true;
935}
936
937template <class Impl>
938Fault
939FullO3CPU<Impl>::getInterrupts()
940{
941 // Check if there are any outstanding interrupts
942 return this->interrupts[0]->getInterrupt(this->threadContexts[0]);
943}
944
945template <class Impl>
946void
947FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
948{
949 // Check for interrupts here. For now can copy the code that
950 // exists within isa_fullsys_traits.hh. Also assume that thread 0
951 // is the one that handles the interrupts.
952 // @todo: Possibly consolidate the interrupt checking code.
953 // @todo: Allow other threads to handle interrupts.
954
955 assert(interrupt != NoFault);
956 this->interrupts[0]->updateIntrInfo(this->threadContexts[0]);
957
958 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
959 this->trap(interrupt, 0, nullptr);
960}
961
962template <class Impl>
963void
964FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
965 const StaticInstPtr &inst)
966{
967 // Pass the thread's TC into the invoke method.
968 fault->invoke(this->threadContexts[tid], inst);
969}
970
971template <class Impl>
972void
973FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault)
974{
975 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
976
977 DPRINTF(Activity,"Activity: syscall() called.\n");
978
979 // Temporarily increase this by one to account for the syscall
980 // instruction.
981 ++(this->thread[tid]->funcExeInst);
982
983 // Execute the actual syscall.
984 this->thread[tid]->syscall(callnum, fault);
985
986 // Decrease funcExeInst by one as the normal commit will handle
987 // incrementing it.
988 --(this->thread[tid]->funcExeInst);
989}
990
991template <class Impl>
992void
993FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
994{
995 thread[tid]->serialize(cp);
996}
997
998template <class Impl>
999void
1000FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
1001{
1002 thread[tid]->unserialize(cp);
1003}
1004
1005template <class Impl>
1006DrainState
1007FullO3CPU<Impl>::drain()
1008{
1009 // If the CPU isn't doing anything, then return immediately.
1010 if (switchedOut())
1011 return DrainState::Drained;
1012
1013 DPRINTF(Drain, "Draining...\n");
1014
1015 // We only need to signal a drain to the commit stage as this
1016 // initiates squashing controls the draining. Once the commit
1017 // stage commits an instruction where it is safe to stop, it'll
1018 // squash the rest of the instructions in the pipeline and force
1019 // the fetch stage to stall. The pipeline will be drained once all
1020 // in-flight instructions have retired.
1021 commit.drain();
1022
1023 // Wake the CPU and record activity so everything can drain out if
1024 // the CPU was not able to immediately drain.
1025 if (!isDrained()) {
1026 wakeCPU();
1027 activityRec.activity();
1028
1029 DPRINTF(Drain, "CPU not drained\n");
1030
1031 return DrainState::Draining;
1032 } else {
1033 DPRINTF(Drain, "CPU is already drained\n");
1034 if (tickEvent.scheduled())
1035 deschedule(tickEvent);
1036
1037 // Flush out any old data from the time buffers. In
1038 // particular, there might be some data in flight from the
1039 // fetch stage that isn't visible in any of the CPU buffers we
1040 // test in isDrained().
1041 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1042 timeBuffer.advance();
1043 fetchQueue.advance();
1044 decodeQueue.advance();
1045 renameQueue.advance();
1046 iewQueue.advance();
1047 }
1048
1049 drainSanityCheck();
1050 return DrainState::Drained;
1051 }
1052}
1053
1054template <class Impl>
1055bool
1056FullO3CPU<Impl>::tryDrain()
1057{
1058 if (drainState() != DrainState::Draining || !isDrained())
1059 return false;
1060
1061 if (tickEvent.scheduled())
1062 deschedule(tickEvent);
1063
1064 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1065 signalDrainDone();
1066
1067 return true;
1068}
1069
1070template <class Impl>
1071void
1072FullO3CPU<Impl>::drainSanityCheck() const
1073{
1074 assert(isDrained());
1075 fetch.drainSanityCheck();
1076 decode.drainSanityCheck();
1077 rename.drainSanityCheck();
1078 iew.drainSanityCheck();
1079 commit.drainSanityCheck();
1080}
1081
1082template <class Impl>
1083bool
1084FullO3CPU<Impl>::isDrained() const
1085{
1086 bool drained(true);
1087
1088 if (!instList.empty() || !removeList.empty()) {
1089 DPRINTF(Drain, "Main CPU structures not drained.\n");
1090 drained = false;
1091 }
1092
1093 if (!fetch.isDrained()) {
1094 DPRINTF(Drain, "Fetch not drained.\n");
1095 drained = false;
1096 }
1097
1098 if (!decode.isDrained()) {
1099 DPRINTF(Drain, "Decode not drained.\n");
1100 drained = false;
1101 }
1102
1103 if (!rename.isDrained()) {
1104 DPRINTF(Drain, "Rename not drained.\n");
1105 drained = false;
1106 }
1107
1108 if (!iew.isDrained()) {
1109 DPRINTF(Drain, "IEW not drained.\n");
1110 drained = false;
1111 }
1112
1113 if (!commit.isDrained()) {
1114 DPRINTF(Drain, "Commit not drained.\n");
1115 drained = false;
1116 }
1117
1118 return drained;
1119}
1120
1121template <class Impl>
1122void
1123FullO3CPU<Impl>::commitDrained(ThreadID tid)
1124{
1125 fetch.drainStall(tid);
1126}
1127
1128template <class Impl>
1129void
1130FullO3CPU<Impl>::drainResume()
1131{
1132 if (switchedOut())
1133 return;
1134
1135 DPRINTF(Drain, "Resuming...\n");
1136 verifyMemoryMode();
1137
1138 fetch.drainResume();
1139 commit.drainResume();
1140
1141 _status = Idle;
1142 for (ThreadID i = 0; i < thread.size(); i++) {
1143 if (thread[i]->status() == ThreadContext::Active) {
1144 DPRINTF(Drain, "Activating thread: %i\n", i);
1145 activateThread(i);
1146 _status = Running;
1147 }
1148 }
1149
1150 assert(!tickEvent.scheduled());
1151 if (_status == Running)
1152 schedule(tickEvent, nextCycle());
1153}
1154
1155template <class Impl>
1156void
1157FullO3CPU<Impl>::switchOut()
1158{
1159 DPRINTF(O3CPU, "Switching out\n");
1160 BaseCPU::switchOut();
1161
1162 activityRec.reset();
1163
1164 _status = SwitchedOut;
1165
1166 if (checker)
1167 checker->switchOut();
1168}
1169
1170template <class Impl>
1171void
1172FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1173{
1174 BaseCPU::takeOverFrom(oldCPU);
1175
1176 fetch.takeOverFrom();
1177 decode.takeOverFrom();
1178 rename.takeOverFrom();
1179 iew.takeOverFrom();
1180 commit.takeOverFrom();
1181
1182 assert(!tickEvent.scheduled());
1183
1184 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1185 if (oldO3CPU)
1186 globalSeqNum = oldO3CPU->globalSeqNum;
1187
1188 lastRunningCycle = curCycle();
1189 _status = Idle;
1190}
1191
1192template <class Impl>
1193void
1194FullO3CPU<Impl>::verifyMemoryMode() const
1195{
1196 if (!system->isTimingMode()) {
1197 fatal("The O3 CPU requires the memory system to be in "
1198 "'timing' mode.\n");
1199 }
1200}
1201
1202template <class Impl>
1203TheISA::MiscReg
1204FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1205{
1206 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1207}
1208
1209template <class Impl>
1210TheISA::MiscReg
1211FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1212{
1213 miscRegfileReads++;
1214 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1215}
1216
1217template <class Impl>
1218void
1219FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1220 const TheISA::MiscReg &val, ThreadID tid)
1221{
1222 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1223}
1224
1225template <class Impl>
1226void
1227FullO3CPU<Impl>::setMiscReg(int misc_reg,
1228 const TheISA::MiscReg &val, ThreadID tid)
1229{
1230 miscRegfileWrites++;
1231 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1232}
1233
1234template <class Impl>
1235uint64_t
1236FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
1237{
1238 intRegfileReads++;
1239 return regFile.readIntReg(phys_reg);
1240}
1241
1242template <class Impl>
1243FloatReg
1244FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg)
1245{
1246 fpRegfileReads++;
1247 return regFile.readFloatReg(phys_reg);
1248}
1249
1250template <class Impl>
1251FloatRegBits
1252FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
1253{
1254 fpRegfileReads++;
1255 return regFile.readFloatRegBits(phys_reg);
1256}
1257
1258template <class Impl>
1259CCReg
1260FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1261{
1262 ccRegfileReads++;
1263 return regFile.readCCReg(phys_reg);
1264}
1265
1266template <class Impl>
1267void
1268FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
1269{
1270 intRegfileWrites++;
1271 regFile.setIntReg(phys_reg, val);
1272}
1273
1274template <class Impl>
1275void
1276FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, FloatReg val)
1277{
1278 fpRegfileWrites++;
1279 regFile.setFloatReg(phys_reg, val);
1280}
1281
1282template <class Impl>
1283void
1284FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
1285{
1286 fpRegfileWrites++;
1287 regFile.setFloatRegBits(phys_reg, val);
1288}
1289
1290template <class Impl>
1291void
1292FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1293{
1294 ccRegfileWrites++;
1295 regFile.setCCReg(phys_reg, val);
1296}
1297
1298template <class Impl>
1299uint64_t
1300FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1301{
1302 intRegfileReads++;
1303 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1304
1305 return regFile.readIntReg(phys_reg);
1306}
1307
1308template <class Impl>
1309float
1310FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1311{
1312 fpRegfileReads++;
1313 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1314
1315 return regFile.readFloatReg(phys_reg);
1316}
1317
1318template <class Impl>
1319uint64_t
1320FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1321{
1322 fpRegfileReads++;
1323 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1324
1325 return regFile.readFloatRegBits(phys_reg);
1326}
1327
1328template <class Impl>
1329CCReg
1330FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1331{
1332 ccRegfileReads++;
1333 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1334
1335 return regFile.readCCReg(phys_reg);
1336}
1337
1338template <class Impl>
1339void
1340FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1341{
1342 intRegfileWrites++;
1343 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1344
1345 regFile.setIntReg(phys_reg, val);
1346}
1347
1348template <class Impl>
1349void
1350FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1351{
1352 fpRegfileWrites++;
1353 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1354
1355 regFile.setFloatReg(phys_reg, val);
1356}
1357
1358template <class Impl>
1359void
1360FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1361{
1362 fpRegfileWrites++;
1363 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1364
1365 regFile.setFloatRegBits(phys_reg, val);
1366}
1367
1368template <class Impl>
1369void
1370FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1371{
1372 ccRegfileWrites++;
1373 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1374
1375 regFile.setCCReg(phys_reg, val);
1376}
1377
1378template <class Impl>
1379TheISA::PCState
1380FullO3CPU<Impl>::pcState(ThreadID tid)
1381{
1382 return commit.pcState(tid);
1383}
1384
1385template <class Impl>
1386void
1387FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1388{
1389 commit.pcState(val, tid);
1390}
1391
1392template <class Impl>
1393Addr
1394FullO3CPU<Impl>::instAddr(ThreadID tid)
1395{
1396 return commit.instAddr(tid);
1397}
1398
1399template <class Impl>
1400Addr
1401FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1402{
1403 return commit.nextInstAddr(tid);
1404}
1405
1406template <class Impl>
1407MicroPC
1408FullO3CPU<Impl>::microPC(ThreadID tid)
1409{
1410 return commit.microPC(tid);
1411}
1412
1413template <class Impl>
1414void
1415FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1416{
1417 this->thread[tid]->noSquashFromTC = true;
1418 this->commit.generateTCEvent(tid);
1419}
1420
1421template <class Impl>
1422typename FullO3CPU<Impl>::ListIt
1423FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1424{
1425 instList.push_back(inst);
1426
1427 return --(instList.end());
1428}
1429
1430template <class Impl>
1431void
1432FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1433{
1434 // Keep an instruction count.
1435 if (!inst->isMicroop() || inst->isLastMicroop()) {
1436 thread[tid]->numInst++;
1437 thread[tid]->numInsts++;
1438 committedInsts[tid]++;
1439 system->totalNumInsts++;
1440
1441 // Check for instruction-count-based events.
1442 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1443 system->instEventQueue.serviceEvents(system->totalNumInsts);
1444 }
1445 thread[tid]->numOp++;
1446 thread[tid]->numOps++;
1447 committedOps[tid]++;
1448
1449 probeInstCommit(inst->staticInst);
1450}
1451
1452template <class Impl>
1453void
1454FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1455{
1456 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1457 "[sn:%lli]\n",
1458 inst->threadNumber, inst->pcState(), inst->seqNum);
1459
1460 removeInstsThisCycle = true;
1461
1462 // Remove the front instruction.
1463 removeList.push(inst->getInstListIt());
1464}
1465
1466template <class Impl>
1467void
1468FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1469{
1470 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1471 " list.\n", tid);
1472
1473 ListIt end_it;
1474
1475 bool rob_empty = false;
1476
1477 if (instList.empty()) {
1478 return;
1479 } else if (rob.isEmpty(tid)) {
1480 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1481 end_it = instList.begin();
1482 rob_empty = true;
1483 } else {
1484 end_it = (rob.readTailInst(tid))->getInstListIt();
1485 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1486 }
1487
1488 removeInstsThisCycle = true;
1489
1490 ListIt inst_it = instList.end();
1491
1492 inst_it--;
1493
1494 // Walk through the instruction list, removing any instructions
1495 // that were inserted after the given instruction iterator, end_it.
1496 while (inst_it != end_it) {
1497 assert(!instList.empty());
1498
1499 squashInstIt(inst_it, tid);
1500
1501 inst_it--;
1502 }
1503
1504 // If the ROB was empty, then we actually need to remove the first
1505 // instruction as well.
1506 if (rob_empty) {
1507 squashInstIt(inst_it, tid);
1508 }
1509}
1510
1511template <class Impl>
1512void
1513FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1514{
1515 assert(!instList.empty());
1516
1517 removeInstsThisCycle = true;
1518
1519 ListIt inst_iter = instList.end();
1520
1521 inst_iter--;
1522
1523 DPRINTF(O3CPU, "Deleting instructions from instruction "
1524 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1525 tid, seq_num, (*inst_iter)->seqNum);
1526
1527 while ((*inst_iter)->seqNum > seq_num) {
1528
1529 bool break_loop = (inst_iter == instList.begin());
1530
1531 squashInstIt(inst_iter, tid);
1532
1533 inst_iter--;
1534
1535 if (break_loop)
1536 break;
1537 }
1538}
1539
1540template <class Impl>
1541inline void
1542FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1543{
1544 if ((*instIt)->threadNumber == tid) {
1545 DPRINTF(O3CPU, "Squashing instruction, "
1546 "[tid:%i] [sn:%lli] PC %s\n",
1547 (*instIt)->threadNumber,
1548 (*instIt)->seqNum,
1549 (*instIt)->pcState());
1550
1551 // Mark it as squashed.
1552 (*instIt)->setSquashed();
1553
1554 // @todo: Formulate a consistent method for deleting
1555 // instructions from the instruction list
1556 // Remove the instruction from the list.
1557 removeList.push(instIt);
1558 }
1559}
1560
1561template <class Impl>
1562void
1563FullO3CPU<Impl>::cleanUpRemovedInsts()
1564{
1565 while (!removeList.empty()) {
1566 DPRINTF(O3CPU, "Removing instruction, "
1567 "[tid:%i] [sn:%lli] PC %s\n",
1568 (*removeList.front())->threadNumber,
1569 (*removeList.front())->seqNum,
1570 (*removeList.front())->pcState());
1571
1572 instList.erase(removeList.front());
1573
1574 removeList.pop();
1575 }
1576
1577 removeInstsThisCycle = false;
1578}
1579/*
1580template <class Impl>
1581void
1582FullO3CPU<Impl>::removeAllInsts()
1583{
1584 instList.clear();
1585}
1586*/
1587template <class Impl>
1588void
1589FullO3CPU<Impl>::dumpInsts()
1590{
1591 int num = 0;
1592
1593 ListIt inst_list_it = instList.begin();
1594
1595 cprintf("Dumping Instruction List\n");
1596
1597 while (inst_list_it != instList.end()) {
1598 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1599 "Squashed:%i\n\n",
1600 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1601 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1602 (*inst_list_it)->isSquashed());
1603 inst_list_it++;
1604 ++num;
1605 }
1606}
1607/*
1608template <class Impl>
1609void
1610FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1611{
1612 iew.wakeDependents(inst);
1613}
1614*/
1615template <class Impl>
1616void
1617FullO3CPU<Impl>::wakeCPU()
1618{
1619 if (activityRec.active() || tickEvent.scheduled()) {
1620 DPRINTF(Activity, "CPU already running.\n");
1621 return;
1622 }
1623
1624 DPRINTF(Activity, "Waking up CPU\n");
1625
1626 Cycles cycles(curCycle() - lastRunningCycle);
1627 // @todo: This is an oddity that is only here to match the stats
1628 if (cycles > 1) {
1629 --cycles;
1630 idleCycles += cycles;
1631 numCycles += cycles;
1632 ppCycles->notify(cycles);
1633 }
1634
1635 schedule(tickEvent, clockEdge());
1636}
1637
1638template <class Impl>
1639void
1640FullO3CPU<Impl>::wakeup(ThreadID tid)
1641{
1642 if (this->thread[tid]->status() != ThreadContext::Suspended)
1643 return;
1644
1645 this->wakeCPU();
1646
1647 DPRINTF(Quiesce, "Suspended Processor woken\n");
1648 this->threadContexts[tid]->activate();
1649}
1650
1651template <class Impl>
1652ThreadID
1653FullO3CPU<Impl>::getFreeTid()
1654{
1655 for (ThreadID tid = 0; tid < numThreads; tid++) {
1656 if (!tids[tid]) {
1657 tids[tid] = true;
1658 return tid;
1659 }
1660 }
1661
1662 return InvalidThreadID;
1663}
1664
1665template <class Impl>
1666void
1667FullO3CPU<Impl>::updateThreadPriority()
1668{
1669 if (activeThreads.size() > 1) {
1670 //DEFAULT TO ROUND ROBIN SCHEME
1671 //e.g. Move highest priority to end of thread list
1672 list<ThreadID>::iterator list_begin = activeThreads.begin();
1673
1674 unsigned high_thread = *list_begin;
1675
1676 activeThreads.erase(list_begin);
1677
1678 activeThreads.push_back(high_thread);
1679 }
1680}
1681
1682// Forward declaration of FullO3CPU.
1683template class FullO3CPU<O3CPUImpl>;
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#include "cpu/o3/cpu.hh"
48
49#include "arch/kernel_stats.hh"
50#include "config/the_isa.hh"
51#include "cpu/activity.hh"
52#include "cpu/checker/cpu.hh"
53#include "cpu/checker/thread_context.hh"
54#include "cpu/o3/isa_specific.hh"
55#include "cpu/o3/thread_context.hh"
56#include "cpu/quiesce_event.hh"
57#include "cpu/simple_thread.hh"
58#include "cpu/thread_context.hh"
59#include "debug/Activity.hh"
60#include "debug/Drain.hh"
61#include "debug/O3CPU.hh"
62#include "debug/Quiesce.hh"
63#include "enums/MemoryMode.hh"
64#include "sim/core.hh"
65#include "sim/full_system.hh"
66#include "sim/process.hh"
67#include "sim/stat_control.hh"
68#include "sim/system.hh"
69
70#if THE_ISA == ALPHA_ISA
71#include "arch/alpha/osfpal.hh"
72#include "debug/Activity.hh"
73
74#endif
75
76struct BaseCPUParams;
77
78using namespace TheISA;
79using namespace std;
80
81BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
82 : BaseCPU(params)
83{
84}
85
86void
87BaseO3CPU::regStats()
88{
89 BaseCPU::regStats();
90}
91
92template<class Impl>
93bool
94FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
95{
96 DPRINTF(O3CPU, "Fetch unit received timing\n");
97 // We shouldn't ever get a cacheable block in Modified state
98 assert(pkt->req->isUncacheable() ||
99 !(pkt->cacheResponding() && !pkt->hasSharers()));
100 fetch->processCacheCompletion(pkt);
101
102 return true;
103}
104
105template<class Impl>
106void
107FullO3CPU<Impl>::IcachePort::recvReqRetry()
108{
109 fetch->recvReqRetry();
110}
111
112template <class Impl>
113bool
114FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
115{
116 return lsq->recvTimingResp(pkt);
117}
118
119template <class Impl>
120void
121FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
122{
123 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
124 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
125 cpu->wakeup(tid);
126 }
127 }
128 lsq->recvTimingSnoopReq(pkt);
129}
130
131template <class Impl>
132void
133FullO3CPU<Impl>::DcachePort::recvReqRetry()
134{
135 lsq->recvReqRetry();
136}
137
138template <class Impl>
139FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
140 : Event(CPU_Tick_Pri), cpu(c)
141{
142}
143
144template <class Impl>
145void
146FullO3CPU<Impl>::TickEvent::process()
147{
148 cpu->tick();
149}
150
151template <class Impl>
152const char *
153FullO3CPU<Impl>::TickEvent::description() const
154{
155 return "FullO3CPU tick";
156}
157
158template <class Impl>
159FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
160 : BaseO3CPU(params),
161 itb(params->itb),
162 dtb(params->dtb),
163 tickEvent(this),
164#ifndef NDEBUG
165 instcount(0),
166#endif
167 removeInstsThisCycle(false),
168 fetch(this, params),
169 decode(this, params),
170 rename(this, params),
171 iew(this, params),
172 commit(this, params),
173
174 regFile(params->numPhysIntRegs,
175 params->numPhysFloatRegs,
176 params->numPhysCCRegs),
177
178 freeList(name() + ".freelist", ®File),
179
180 rob(this, params),
181
182 scoreboard(name() + ".scoreboard",
183 regFile.totalNumPhysRegs()),
184
185 isa(numThreads, NULL),
186
187 icachePort(&fetch, this),
188 dcachePort(&iew.ldstQueue, this),
189
190 timeBuffer(params->backComSize, params->forwardComSize),
191 fetchQueue(params->backComSize, params->forwardComSize),
192 decodeQueue(params->backComSize, params->forwardComSize),
193 renameQueue(params->backComSize, params->forwardComSize),
194 iewQueue(params->backComSize, params->forwardComSize),
195 activityRec(name(), NumStages,
196 params->backComSize + params->forwardComSize,
197 params->activity),
198
199 globalSeqNum(1),
200 system(params->system),
201 lastRunningCycle(curCycle())
202{
203 if (!params->switched_out) {
204 _status = Running;
205 } else {
206 _status = SwitchedOut;
207 }
208
209 if (params->checker) {
210 BaseCPU *temp_checker = params->checker;
211 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
212 checker->setIcachePort(&icachePort);
213 checker->setSystem(params->system);
214 } else {
215 checker = NULL;
216 }
217
218 if (!FullSystem) {
219 thread.resize(numThreads);
220 tids.resize(numThreads);
221 }
222
223 // The stages also need their CPU pointer setup. However this
224 // must be done at the upper level CPU because they have pointers
225 // to the upper level CPU, and not this FullO3CPU.
226
227 // Set up Pointers to the activeThreads list for each stage
228 fetch.setActiveThreads(&activeThreads);
229 decode.setActiveThreads(&activeThreads);
230 rename.setActiveThreads(&activeThreads);
231 iew.setActiveThreads(&activeThreads);
232 commit.setActiveThreads(&activeThreads);
233
234 // Give each of the stages the time buffer they will use.
235 fetch.setTimeBuffer(&timeBuffer);
236 decode.setTimeBuffer(&timeBuffer);
237 rename.setTimeBuffer(&timeBuffer);
238 iew.setTimeBuffer(&timeBuffer);
239 commit.setTimeBuffer(&timeBuffer);
240
241 // Also setup each of the stages' queues.
242 fetch.setFetchQueue(&fetchQueue);
243 decode.setFetchQueue(&fetchQueue);
244 commit.setFetchQueue(&fetchQueue);
245 decode.setDecodeQueue(&decodeQueue);
246 rename.setDecodeQueue(&decodeQueue);
247 rename.setRenameQueue(&renameQueue);
248 iew.setRenameQueue(&renameQueue);
249 iew.setIEWQueue(&iewQueue);
250 commit.setIEWQueue(&iewQueue);
251 commit.setRenameQueue(&renameQueue);
252
253 commit.setIEWStage(&iew);
254 rename.setIEWStage(&iew);
255 rename.setCommitStage(&commit);
256
257 ThreadID active_threads;
258 if (FullSystem) {
259 active_threads = 1;
260 } else {
261 active_threads = params->workload.size();
262
263 if (active_threads > Impl::MaxThreads) {
264 panic("Workload Size too large. Increase the 'MaxThreads' "
265 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
266 "or edit your workload size.");
267 }
268 }
269
270 //Make Sure That this a Valid Architeture
271 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
272 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
273 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
274
275 rename.setScoreboard(&scoreboard);
276 iew.setScoreboard(&scoreboard);
277
278 // Setup the rename map for whichever stages need it.
279 for (ThreadID tid = 0; tid < numThreads; tid++) {
280 isa[tid] = params->isa[tid];
281
282 // Only Alpha has an FP zero register, so for other ISAs we
283 // use an invalid FP register index to avoid special treatment
284 // of any valid FP reg.
285 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
286 RegIndex fpZeroReg =
287 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
288
289 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
290 &freeList);
291
292 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
293 &freeList);
294 }
295
296 // Initialize rename map to assign physical registers to the
297 // architectural registers for active threads only.
298 for (ThreadID tid = 0; tid < active_threads; tid++) {
299 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
300 // Note that we can't use the rename() method because we don't
301 // want special treatment for the zero register at this point
302 PhysRegIdPtr phys_reg = freeList.getIntReg();
303 renameMap[tid].setIntEntry(ridx, phys_reg);
304 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
305 }
306
307 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
308 PhysRegIdPtr phys_reg = freeList.getFloatReg();
309 renameMap[tid].setFloatEntry(ridx, phys_reg);
310 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
311 }
312
313 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
314 PhysRegIdPtr phys_reg = freeList.getCCReg();
315 renameMap[tid].setCCEntry(ridx, phys_reg);
316 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
317 }
318 }
319
320 rename.setRenameMap(renameMap);
321 commit.setRenameMap(commitRenameMap);
322 rename.setFreeList(&freeList);
323
324 // Setup the ROB for whichever stages need it.
325 commit.setROB(&rob);
326
327 lastActivatedCycle = 0;
328#if 0
329 // Give renameMap & rename stage access to the freeList;
330 for (ThreadID tid = 0; tid < numThreads; tid++)
331 globalSeqNum[tid] = 1;
332#endif
333
334 DPRINTF(O3CPU, "Creating O3CPU object.\n");
335
336 // Setup any thread state.
337 this->thread.resize(this->numThreads);
338
339 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
340 if (FullSystem) {
341 // SMT is not supported in FS mode yet.
342 assert(this->numThreads == 1);
343 this->thread[tid] = new Thread(this, 0, NULL);
344 } else {
345 if (tid < params->workload.size()) {
346 DPRINTF(O3CPU, "Workload[%i] process is %#x",
347 tid, this->thread[tid]);
348 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
349 (typename Impl::O3CPU *)(this),
350 tid, params->workload[tid]);
351
352 //usedTids[tid] = true;
353 //threadMap[tid] = tid;
354 } else {
355 //Allocate Empty thread so M5 can use later
356 //when scheduling threads to CPU
357 Process* dummy_proc = NULL;
358
359 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
360 (typename Impl::O3CPU *)(this),
361 tid, dummy_proc);
362 //usedTids[tid] = false;
363 }
364 }
365
366 ThreadContext *tc;
367
368 // Setup the TC that will serve as the interface to the threads/CPU.
369 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
370
371 tc = o3_tc;
372
373 // If we're using a checker, then the TC should be the
374 // CheckerThreadContext.
375 if (params->checker) {
376 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
377 o3_tc, this->checker);
378 }
379
380 o3_tc->cpu = (typename Impl::O3CPU *)(this);
381 assert(o3_tc->cpu);
382 o3_tc->thread = this->thread[tid];
383
384 // Setup quiesce event.
385 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
386
387 // Give the thread the TC.
388 this->thread[tid]->tc = tc;
389
390 // Add the TC to the CPU's list of TC's.
391 this->threadContexts.push_back(tc);
392 }
393
394 // FullO3CPU always requires an interrupt controller.
395 if (!params->switched_out && interrupts.empty()) {
396 fatal("FullO3CPU %s has no interrupt controller.\n"
397 "Ensure createInterruptController() is called.\n", name());
398 }
399
400 for (ThreadID tid = 0; tid < this->numThreads; tid++)
401 this->thread[tid]->setFuncExeInst(0);
402}
403
404template <class Impl>
405FullO3CPU<Impl>::~FullO3CPU()
406{
407}
408
409template <class Impl>
410void
411FullO3CPU<Impl>::regProbePoints()
412{
413 BaseCPU::regProbePoints();
414
415 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
416 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
417
418 fetch.regProbePoints();
419 rename.regProbePoints();
420 iew.regProbePoints();
421 commit.regProbePoints();
422}
423
424template <class Impl>
425void
426FullO3CPU<Impl>::regStats()
427{
428 BaseO3CPU::regStats();
429
430 // Register any of the O3CPU's stats here.
431 timesIdled
432 .name(name() + ".timesIdled")
433 .desc("Number of times that the entire CPU went into an idle state and"
434 " unscheduled itself")
435 .prereq(timesIdled);
436
437 idleCycles
438 .name(name() + ".idleCycles")
439 .desc("Total number of cycles that the CPU has spent unscheduled due "
440 "to idling")
441 .prereq(idleCycles);
442
443 quiesceCycles
444 .name(name() + ".quiesceCycles")
445 .desc("Total number of cycles that CPU has spent quiesced or waiting "
446 "for an interrupt")
447 .prereq(quiesceCycles);
448
449 // Number of Instructions simulated
450 // --------------------------------
451 // Should probably be in Base CPU but need templated
452 // MaxThreads so put in here instead
453 committedInsts
454 .init(numThreads)
455 .name(name() + ".committedInsts")
456 .desc("Number of Instructions Simulated")
457 .flags(Stats::total);
458
459 committedOps
460 .init(numThreads)
461 .name(name() + ".committedOps")
462 .desc("Number of Ops (including micro ops) Simulated")
463 .flags(Stats::total);
464
465 cpi
466 .name(name() + ".cpi")
467 .desc("CPI: Cycles Per Instruction")
468 .precision(6);
469 cpi = numCycles / committedInsts;
470
471 totalCpi
472 .name(name() + ".cpi_total")
473 .desc("CPI: Total CPI of All Threads")
474 .precision(6);
475 totalCpi = numCycles / sum(committedInsts);
476
477 ipc
478 .name(name() + ".ipc")
479 .desc("IPC: Instructions Per Cycle")
480 .precision(6);
481 ipc = committedInsts / numCycles;
482
483 totalIpc
484 .name(name() + ".ipc_total")
485 .desc("IPC: Total IPC of All Threads")
486 .precision(6);
487 totalIpc = sum(committedInsts) / numCycles;
488
489 this->fetch.regStats();
490 this->decode.regStats();
491 this->rename.regStats();
492 this->iew.regStats();
493 this->commit.regStats();
494 this->rob.regStats();
495
496 intRegfileReads
497 .name(name() + ".int_regfile_reads")
498 .desc("number of integer regfile reads")
499 .prereq(intRegfileReads);
500
501 intRegfileWrites
502 .name(name() + ".int_regfile_writes")
503 .desc("number of integer regfile writes")
504 .prereq(intRegfileWrites);
505
506 fpRegfileReads
507 .name(name() + ".fp_regfile_reads")
508 .desc("number of floating regfile reads")
509 .prereq(fpRegfileReads);
510
511 fpRegfileWrites
512 .name(name() + ".fp_regfile_writes")
513 .desc("number of floating regfile writes")
514 .prereq(fpRegfileWrites);
515
516 ccRegfileReads
517 .name(name() + ".cc_regfile_reads")
518 .desc("number of cc regfile reads")
519 .prereq(ccRegfileReads);
520
521 ccRegfileWrites
522 .name(name() + ".cc_regfile_writes")
523 .desc("number of cc regfile writes")
524 .prereq(ccRegfileWrites);
525
526 miscRegfileReads
527 .name(name() + ".misc_regfile_reads")
528 .desc("number of misc regfile reads")
529 .prereq(miscRegfileReads);
530
531 miscRegfileWrites
532 .name(name() + ".misc_regfile_writes")
533 .desc("number of misc regfile writes")
534 .prereq(miscRegfileWrites);
535}
536
537template <class Impl>
538void
539FullO3CPU<Impl>::tick()
540{
541 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
542 assert(!switchedOut());
543 assert(drainState() != DrainState::Drained);
544
545 ++numCycles;
546 ppCycles->notify(1);
547
548// activity = false;
549
550 //Tick each of the stages
551 fetch.tick();
552
553 decode.tick();
554
555 rename.tick();
556
557 iew.tick();
558
559 commit.tick();
560
561 // Now advance the time buffers
562 timeBuffer.advance();
563
564 fetchQueue.advance();
565 decodeQueue.advance();
566 renameQueue.advance();
567 iewQueue.advance();
568
569 activityRec.advance();
570
571 if (removeInstsThisCycle) {
572 cleanUpRemovedInsts();
573 }
574
575 if (!tickEvent.scheduled()) {
576 if (_status == SwitchedOut) {
577 DPRINTF(O3CPU, "Switched out!\n");
578 // increment stat
579 lastRunningCycle = curCycle();
580 } else if (!activityRec.active() || _status == Idle) {
581 DPRINTF(O3CPU, "Idle!\n");
582 lastRunningCycle = curCycle();
583 timesIdled++;
584 } else {
585 schedule(tickEvent, clockEdge(Cycles(1)));
586 DPRINTF(O3CPU, "Scheduling next tick!\n");
587 }
588 }
589
590 if (!FullSystem)
591 updateThreadPriority();
592
593 tryDrain();
594}
595
596template <class Impl>
597void
598FullO3CPU<Impl>::init()
599{
600 BaseCPU::init();
601
602 for (ThreadID tid = 0; tid < numThreads; ++tid) {
603 // Set noSquashFromTC so that the CPU doesn't squash when initially
604 // setting up registers.
605 thread[tid]->noSquashFromTC = true;
606 // Initialise the ThreadContext's memory proxies
607 thread[tid]->initMemProxies(thread[tid]->getTC());
608 }
609
610 if (FullSystem && !params()->switched_out) {
611 for (ThreadID tid = 0; tid < numThreads; tid++) {
612 ThreadContext *src_tc = threadContexts[tid];
613 TheISA::initCPU(src_tc, src_tc->contextId());
614 }
615 }
616
617 // Clear noSquashFromTC.
618 for (int tid = 0; tid < numThreads; ++tid)
619 thread[tid]->noSquashFromTC = false;
620
621 commit.setThreads(thread);
622}
623
624template <class Impl>
625void
626FullO3CPU<Impl>::startup()
627{
628 BaseCPU::startup();
629 for (int tid = 0; tid < numThreads; ++tid)
630 isa[tid]->startup(threadContexts[tid]);
631
632 fetch.startupStage();
633 decode.startupStage();
634 iew.startupStage();
635 rename.startupStage();
636 commit.startupStage();
637}
638
639template <class Impl>
640void
641FullO3CPU<Impl>::activateThread(ThreadID tid)
642{
643 list<ThreadID>::iterator isActive =
644 std::find(activeThreads.begin(), activeThreads.end(), tid);
645
646 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
647 assert(!switchedOut());
648
649 if (isActive == activeThreads.end()) {
650 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
651 tid);
652
653 activeThreads.push_back(tid);
654 }
655}
656
657template <class Impl>
658void
659FullO3CPU<Impl>::deactivateThread(ThreadID tid)
660{
661 //Remove From Active List, if Active
662 list<ThreadID>::iterator thread_it =
663 std::find(activeThreads.begin(), activeThreads.end(), tid);
664
665 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
666 assert(!switchedOut());
667
668 if (thread_it != activeThreads.end()) {
669 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
670 tid);
671 activeThreads.erase(thread_it);
672 }
673
674 fetch.deactivateThread(tid);
675 commit.deactivateThread(tid);
676}
677
678template <class Impl>
679Counter
680FullO3CPU<Impl>::totalInsts() const
681{
682 Counter total(0);
683
684 ThreadID size = thread.size();
685 for (ThreadID i = 0; i < size; i++)
686 total += thread[i]->numInst;
687
688 return total;
689}
690
691template <class Impl>
692Counter
693FullO3CPU<Impl>::totalOps() const
694{
695 Counter total(0);
696
697 ThreadID size = thread.size();
698 for (ThreadID i = 0; i < size; i++)
699 total += thread[i]->numOp;
700
701 return total;
702}
703
704template <class Impl>
705void
706FullO3CPU<Impl>::activateContext(ThreadID tid)
707{
708 assert(!switchedOut());
709
710 // Needs to set each stage to running as well.
711 activateThread(tid);
712
713 // We don't want to wake the CPU if it is drained. In that case,
714 // we just want to flag the thread as active and schedule the tick
715 // event from drainResume() instead.
716 if (drainState() == DrainState::Drained)
717 return;
718
719 // If we are time 0 or if the last activation time is in the past,
720 // schedule the next tick and wake up the fetch unit
721 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
722 scheduleTickEvent(Cycles(0));
723
724 // Be sure to signal that there's some activity so the CPU doesn't
725 // deschedule itself.
726 activityRec.activity();
727 fetch.wakeFromQuiesce();
728
729 Cycles cycles(curCycle() - lastRunningCycle);
730 // @todo: This is an oddity that is only here to match the stats
731 if (cycles != 0)
732 --cycles;
733 quiesceCycles += cycles;
734
735 lastActivatedCycle = curTick();
736
737 _status = Running;
738
739 BaseCPU::activateContext(tid);
740 }
741}
742
743template <class Impl>
744void
745FullO3CPU<Impl>::suspendContext(ThreadID tid)
746{
747 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
748 assert(!switchedOut());
749
750 deactivateThread(tid);
751
752 // If this was the last thread then unschedule the tick event.
753 if (activeThreads.size() == 0) {
754 unscheduleTickEvent();
755 lastRunningCycle = curCycle();
756 _status = Idle;
757 }
758
759 DPRINTF(Quiesce, "Suspending Context\n");
760
761 BaseCPU::suspendContext(tid);
762}
763
764template <class Impl>
765void
766FullO3CPU<Impl>::haltContext(ThreadID tid)
767{
768 //For now, this is the same as deallocate
769 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
770 assert(!switchedOut());
771
772 deactivateThread(tid);
773 removeThread(tid);
774}
775
776template <class Impl>
777void
778FullO3CPU<Impl>::insertThread(ThreadID tid)
779{
780 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
781 // Will change now that the PC and thread state is internal to the CPU
782 // and not in the ThreadContext.
783 ThreadContext *src_tc;
784 if (FullSystem)
785 src_tc = system->threadContexts[tid];
786 else
787 src_tc = tcBase(tid);
788
789 //Bind Int Regs to Rename Map
790
791 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
792 reg_id.regIdx++) {
793 PhysRegIdPtr phys_reg = freeList.getIntReg();
794 renameMap[tid].setEntry(reg_id, phys_reg);
795 scoreboard.setReg(phys_reg);
796 }
797
798 //Bind Float Regs to Rename Map
799 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
800 reg_id.regIdx++) {
801 PhysRegIdPtr phys_reg = freeList.getFloatReg();
802 renameMap[tid].setEntry(reg_id, phys_reg);
803 scoreboard.setReg(phys_reg);
804 }
805
806 //Bind condition-code Regs to Rename Map
807 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
808 reg_id.regIdx++) {
809 PhysRegIdPtr phys_reg = freeList.getCCReg();
810 renameMap[tid].setEntry(reg_id, phys_reg);
811 scoreboard.setReg(phys_reg);
812 }
813
814 //Copy Thread Data Into RegFile
815 //this->copyFromTC(tid);
816
817 //Set PC/NPC/NNPC
818 pcState(src_tc->pcState(), tid);
819
820 src_tc->setStatus(ThreadContext::Active);
821
822 activateContext(tid);
823
824 //Reset ROB/IQ/LSQ Entries
825 commit.rob->resetEntries();
826 iew.resetEntries();
827}
828
829template <class Impl>
830void
831FullO3CPU<Impl>::removeThread(ThreadID tid)
832{
833 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
834
835 // Copy Thread Data From RegFile
836 // If thread is suspended, it might be re-allocated
837 // this->copyToTC(tid);
838
839
840 // @todo: 2-27-2008: Fix how we free up rename mappings
841 // here to alleviate the case for double-freeing registers
842 // in SMT workloads.
843
844 // Unbind Int Regs from Rename Map
845 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
846 reg_id.regIdx++) {
847 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
848 scoreboard.unsetReg(phys_reg);
849 freeList.addReg(phys_reg);
850 }
851
852 // Unbind Float Regs from Rename Map
853 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
854 reg_id.regIdx++) {
855 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
856 scoreboard.unsetReg(phys_reg);
857 freeList.addReg(phys_reg);
858 }
859
860 // Unbind condition-code Regs from Rename Map
861 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
862 reg_id.regIdx++) {
863 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
864 scoreboard.unsetReg(phys_reg);
865 freeList.addReg(phys_reg);
866 }
867
868 // Squash Throughout Pipeline
869 DynInstPtr inst = commit.rob->readHeadInst(tid);
870 InstSeqNum squash_seq_num = inst->seqNum;
871 fetch.squash(0, squash_seq_num, inst, tid);
872 decode.squash(tid);
873 rename.squash(squash_seq_num, tid);
874 iew.squash(tid);
875 iew.ldstQueue.squash(squash_seq_num, tid);
876 commit.rob->squash(squash_seq_num, tid);
877
878
879 assert(iew.instQueue.getCount(tid) == 0);
880 assert(iew.ldstQueue.getCount(tid) == 0);
881
882 // Reset ROB/IQ/LSQ Entries
883
884 // Commented out for now. This should be possible to do by
885 // telling all the pipeline stages to drain first, and then
886 // checking until the drain completes. Once the pipeline is
887 // drained, call resetEntries(). - 10-09-06 ktlim
888/*
889 if (activeThreads.size() >= 1) {
890 commit.rob->resetEntries();
891 iew.resetEntries();
892 }
893*/
894}
895
896template <class Impl>
897Fault
898FullO3CPU<Impl>::hwrei(ThreadID tid)
899{
900#if THE_ISA == ALPHA_ISA
901 // Need to clear the lock flag upon returning from an interrupt.
902 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
903
904 this->thread[tid]->kernelStats->hwrei();
905
906 // FIXME: XXX check for interrupts? XXX
907#endif
908 return NoFault;
909}
910
911template <class Impl>
912bool
913FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
914{
915#if THE_ISA == ALPHA_ISA
916 if (this->thread[tid]->kernelStats)
917 this->thread[tid]->kernelStats->callpal(palFunc,
918 this->threadContexts[tid]);
919
920 switch (palFunc) {
921 case PAL::halt:
922 halt();
923 if (--System::numSystemsRunning == 0)
924 exitSimLoop("all cpus halted");
925 break;
926
927 case PAL::bpt:
928 case PAL::bugchk:
929 if (this->system->breakpoint())
930 return false;
931 break;
932 }
933#endif
934 return true;
935}
936
937template <class Impl>
938Fault
939FullO3CPU<Impl>::getInterrupts()
940{
941 // Check if there are any outstanding interrupts
942 return this->interrupts[0]->getInterrupt(this->threadContexts[0]);
943}
944
945template <class Impl>
946void
947FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
948{
949 // Check for interrupts here. For now can copy the code that
950 // exists within isa_fullsys_traits.hh. Also assume that thread 0
951 // is the one that handles the interrupts.
952 // @todo: Possibly consolidate the interrupt checking code.
953 // @todo: Allow other threads to handle interrupts.
954
955 assert(interrupt != NoFault);
956 this->interrupts[0]->updateIntrInfo(this->threadContexts[0]);
957
958 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
959 this->trap(interrupt, 0, nullptr);
960}
961
962template <class Impl>
963void
964FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
965 const StaticInstPtr &inst)
966{
967 // Pass the thread's TC into the invoke method.
968 fault->invoke(this->threadContexts[tid], inst);
969}
970
971template <class Impl>
972void
973FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault)
974{
975 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
976
977 DPRINTF(Activity,"Activity: syscall() called.\n");
978
979 // Temporarily increase this by one to account for the syscall
980 // instruction.
981 ++(this->thread[tid]->funcExeInst);
982
983 // Execute the actual syscall.
984 this->thread[tid]->syscall(callnum, fault);
985
986 // Decrease funcExeInst by one as the normal commit will handle
987 // incrementing it.
988 --(this->thread[tid]->funcExeInst);
989}
990
991template <class Impl>
992void
993FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
994{
995 thread[tid]->serialize(cp);
996}
997
998template <class Impl>
999void
1000FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
1001{
1002 thread[tid]->unserialize(cp);
1003}
1004
1005template <class Impl>
1006DrainState
1007FullO3CPU<Impl>::drain()
1008{
1009 // If the CPU isn't doing anything, then return immediately.
1010 if (switchedOut())
1011 return DrainState::Drained;
1012
1013 DPRINTF(Drain, "Draining...\n");
1014
1015 // We only need to signal a drain to the commit stage as this
1016 // initiates squashing controls the draining. Once the commit
1017 // stage commits an instruction where it is safe to stop, it'll
1018 // squash the rest of the instructions in the pipeline and force
1019 // the fetch stage to stall. The pipeline will be drained once all
1020 // in-flight instructions have retired.
1021 commit.drain();
1022
1023 // Wake the CPU and record activity so everything can drain out if
1024 // the CPU was not able to immediately drain.
1025 if (!isDrained()) {
1026 wakeCPU();
1027 activityRec.activity();
1028
1029 DPRINTF(Drain, "CPU not drained\n");
1030
1031 return DrainState::Draining;
1032 } else {
1033 DPRINTF(Drain, "CPU is already drained\n");
1034 if (tickEvent.scheduled())
1035 deschedule(tickEvent);
1036
1037 // Flush out any old data from the time buffers. In
1038 // particular, there might be some data in flight from the
1039 // fetch stage that isn't visible in any of the CPU buffers we
1040 // test in isDrained().
1041 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1042 timeBuffer.advance();
1043 fetchQueue.advance();
1044 decodeQueue.advance();
1045 renameQueue.advance();
1046 iewQueue.advance();
1047 }
1048
1049 drainSanityCheck();
1050 return DrainState::Drained;
1051 }
1052}
1053
1054template <class Impl>
1055bool
1056FullO3CPU<Impl>::tryDrain()
1057{
1058 if (drainState() != DrainState::Draining || !isDrained())
1059 return false;
1060
1061 if (tickEvent.scheduled())
1062 deschedule(tickEvent);
1063
1064 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1065 signalDrainDone();
1066
1067 return true;
1068}
1069
1070template <class Impl>
1071void
1072FullO3CPU<Impl>::drainSanityCheck() const
1073{
1074 assert(isDrained());
1075 fetch.drainSanityCheck();
1076 decode.drainSanityCheck();
1077 rename.drainSanityCheck();
1078 iew.drainSanityCheck();
1079 commit.drainSanityCheck();
1080}
1081
1082template <class Impl>
1083bool
1084FullO3CPU<Impl>::isDrained() const
1085{
1086 bool drained(true);
1087
1088 if (!instList.empty() || !removeList.empty()) {
1089 DPRINTF(Drain, "Main CPU structures not drained.\n");
1090 drained = false;
1091 }
1092
1093 if (!fetch.isDrained()) {
1094 DPRINTF(Drain, "Fetch not drained.\n");
1095 drained = false;
1096 }
1097
1098 if (!decode.isDrained()) {
1099 DPRINTF(Drain, "Decode not drained.\n");
1100 drained = false;
1101 }
1102
1103 if (!rename.isDrained()) {
1104 DPRINTF(Drain, "Rename not drained.\n");
1105 drained = false;
1106 }
1107
1108 if (!iew.isDrained()) {
1109 DPRINTF(Drain, "IEW not drained.\n");
1110 drained = false;
1111 }
1112
1113 if (!commit.isDrained()) {
1114 DPRINTF(Drain, "Commit not drained.\n");
1115 drained = false;
1116 }
1117
1118 return drained;
1119}
1120
1121template <class Impl>
1122void
1123FullO3CPU<Impl>::commitDrained(ThreadID tid)
1124{
1125 fetch.drainStall(tid);
1126}
1127
1128template <class Impl>
1129void
1130FullO3CPU<Impl>::drainResume()
1131{
1132 if (switchedOut())
1133 return;
1134
1135 DPRINTF(Drain, "Resuming...\n");
1136 verifyMemoryMode();
1137
1138 fetch.drainResume();
1139 commit.drainResume();
1140
1141 _status = Idle;
1142 for (ThreadID i = 0; i < thread.size(); i++) {
1143 if (thread[i]->status() == ThreadContext::Active) {
1144 DPRINTF(Drain, "Activating thread: %i\n", i);
1145 activateThread(i);
1146 _status = Running;
1147 }
1148 }
1149
1150 assert(!tickEvent.scheduled());
1151 if (_status == Running)
1152 schedule(tickEvent, nextCycle());
1153}
1154
1155template <class Impl>
1156void
1157FullO3CPU<Impl>::switchOut()
1158{
1159 DPRINTF(O3CPU, "Switching out\n");
1160 BaseCPU::switchOut();
1161
1162 activityRec.reset();
1163
1164 _status = SwitchedOut;
1165
1166 if (checker)
1167 checker->switchOut();
1168}
1169
1170template <class Impl>
1171void
1172FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1173{
1174 BaseCPU::takeOverFrom(oldCPU);
1175
1176 fetch.takeOverFrom();
1177 decode.takeOverFrom();
1178 rename.takeOverFrom();
1179 iew.takeOverFrom();
1180 commit.takeOverFrom();
1181
1182 assert(!tickEvent.scheduled());
1183
1184 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1185 if (oldO3CPU)
1186 globalSeqNum = oldO3CPU->globalSeqNum;
1187
1188 lastRunningCycle = curCycle();
1189 _status = Idle;
1190}
1191
1192template <class Impl>
1193void
1194FullO3CPU<Impl>::verifyMemoryMode() const
1195{
1196 if (!system->isTimingMode()) {
1197 fatal("The O3 CPU requires the memory system to be in "
1198 "'timing' mode.\n");
1199 }
1200}
1201
1202template <class Impl>
1203TheISA::MiscReg
1204FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1205{
1206 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1207}
1208
1209template <class Impl>
1210TheISA::MiscReg
1211FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1212{
1213 miscRegfileReads++;
1214 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1215}
1216
1217template <class Impl>
1218void
1219FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1220 const TheISA::MiscReg &val, ThreadID tid)
1221{
1222 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1223}
1224
1225template <class Impl>
1226void
1227FullO3CPU<Impl>::setMiscReg(int misc_reg,
1228 const TheISA::MiscReg &val, ThreadID tid)
1229{
1230 miscRegfileWrites++;
1231 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1232}
1233
1234template <class Impl>
1235uint64_t
1236FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
1237{
1238 intRegfileReads++;
1239 return regFile.readIntReg(phys_reg);
1240}
1241
1242template <class Impl>
1243FloatReg
1244FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg)
1245{
1246 fpRegfileReads++;
1247 return regFile.readFloatReg(phys_reg);
1248}
1249
1250template <class Impl>
1251FloatRegBits
1252FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
1253{
1254 fpRegfileReads++;
1255 return regFile.readFloatRegBits(phys_reg);
1256}
1257
1258template <class Impl>
1259CCReg
1260FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1261{
1262 ccRegfileReads++;
1263 return regFile.readCCReg(phys_reg);
1264}
1265
1266template <class Impl>
1267void
1268FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
1269{
1270 intRegfileWrites++;
1271 regFile.setIntReg(phys_reg, val);
1272}
1273
1274template <class Impl>
1275void
1276FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, FloatReg val)
1277{
1278 fpRegfileWrites++;
1279 regFile.setFloatReg(phys_reg, val);
1280}
1281
1282template <class Impl>
1283void
1284FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
1285{
1286 fpRegfileWrites++;
1287 regFile.setFloatRegBits(phys_reg, val);
1288}
1289
1290template <class Impl>
1291void
1292FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1293{
1294 ccRegfileWrites++;
1295 regFile.setCCReg(phys_reg, val);
1296}
1297
1298template <class Impl>
1299uint64_t
1300FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1301{
1302 intRegfileReads++;
1303 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1304
1305 return regFile.readIntReg(phys_reg);
1306}
1307
1308template <class Impl>
1309float
1310FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1311{
1312 fpRegfileReads++;
1313 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1314
1315 return regFile.readFloatReg(phys_reg);
1316}
1317
1318template <class Impl>
1319uint64_t
1320FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1321{
1322 fpRegfileReads++;
1323 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1324
1325 return regFile.readFloatRegBits(phys_reg);
1326}
1327
1328template <class Impl>
1329CCReg
1330FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1331{
1332 ccRegfileReads++;
1333 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1334
1335 return regFile.readCCReg(phys_reg);
1336}
1337
1338template <class Impl>
1339void
1340FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1341{
1342 intRegfileWrites++;
1343 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1344
1345 regFile.setIntReg(phys_reg, val);
1346}
1347
1348template <class Impl>
1349void
1350FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1351{
1352 fpRegfileWrites++;
1353 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1354
1355 regFile.setFloatReg(phys_reg, val);
1356}
1357
1358template <class Impl>
1359void
1360FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1361{
1362 fpRegfileWrites++;
1363 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1364
1365 regFile.setFloatRegBits(phys_reg, val);
1366}
1367
1368template <class Impl>
1369void
1370FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1371{
1372 ccRegfileWrites++;
1373 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1374
1375 regFile.setCCReg(phys_reg, val);
1376}
1377
1378template <class Impl>
1379TheISA::PCState
1380FullO3CPU<Impl>::pcState(ThreadID tid)
1381{
1382 return commit.pcState(tid);
1383}
1384
1385template <class Impl>
1386void
1387FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1388{
1389 commit.pcState(val, tid);
1390}
1391
1392template <class Impl>
1393Addr
1394FullO3CPU<Impl>::instAddr(ThreadID tid)
1395{
1396 return commit.instAddr(tid);
1397}
1398
1399template <class Impl>
1400Addr
1401FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1402{
1403 return commit.nextInstAddr(tid);
1404}
1405
1406template <class Impl>
1407MicroPC
1408FullO3CPU<Impl>::microPC(ThreadID tid)
1409{
1410 return commit.microPC(tid);
1411}
1412
1413template <class Impl>
1414void
1415FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1416{
1417 this->thread[tid]->noSquashFromTC = true;
1418 this->commit.generateTCEvent(tid);
1419}
1420
1421template <class Impl>
1422typename FullO3CPU<Impl>::ListIt
1423FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1424{
1425 instList.push_back(inst);
1426
1427 return --(instList.end());
1428}
1429
1430template <class Impl>
1431void
1432FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1433{
1434 // Keep an instruction count.
1435 if (!inst->isMicroop() || inst->isLastMicroop()) {
1436 thread[tid]->numInst++;
1437 thread[tid]->numInsts++;
1438 committedInsts[tid]++;
1439 system->totalNumInsts++;
1440
1441 // Check for instruction-count-based events.
1442 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1443 system->instEventQueue.serviceEvents(system->totalNumInsts);
1444 }
1445 thread[tid]->numOp++;
1446 thread[tid]->numOps++;
1447 committedOps[tid]++;
1448
1449 probeInstCommit(inst->staticInst);
1450}
1451
1452template <class Impl>
1453void
1454FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1455{
1456 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1457 "[sn:%lli]\n",
1458 inst->threadNumber, inst->pcState(), inst->seqNum);
1459
1460 removeInstsThisCycle = true;
1461
1462 // Remove the front instruction.
1463 removeList.push(inst->getInstListIt());
1464}
1465
1466template <class Impl>
1467void
1468FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1469{
1470 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1471 " list.\n", tid);
1472
1473 ListIt end_it;
1474
1475 bool rob_empty = false;
1476
1477 if (instList.empty()) {
1478 return;
1479 } else if (rob.isEmpty(tid)) {
1480 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1481 end_it = instList.begin();
1482 rob_empty = true;
1483 } else {
1484 end_it = (rob.readTailInst(tid))->getInstListIt();
1485 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1486 }
1487
1488 removeInstsThisCycle = true;
1489
1490 ListIt inst_it = instList.end();
1491
1492 inst_it--;
1493
1494 // Walk through the instruction list, removing any instructions
1495 // that were inserted after the given instruction iterator, end_it.
1496 while (inst_it != end_it) {
1497 assert(!instList.empty());
1498
1499 squashInstIt(inst_it, tid);
1500
1501 inst_it--;
1502 }
1503
1504 // If the ROB was empty, then we actually need to remove the first
1505 // instruction as well.
1506 if (rob_empty) {
1507 squashInstIt(inst_it, tid);
1508 }
1509}
1510
1511template <class Impl>
1512void
1513FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1514{
1515 assert(!instList.empty());
1516
1517 removeInstsThisCycle = true;
1518
1519 ListIt inst_iter = instList.end();
1520
1521 inst_iter--;
1522
1523 DPRINTF(O3CPU, "Deleting instructions from instruction "
1524 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1525 tid, seq_num, (*inst_iter)->seqNum);
1526
1527 while ((*inst_iter)->seqNum > seq_num) {
1528
1529 bool break_loop = (inst_iter == instList.begin());
1530
1531 squashInstIt(inst_iter, tid);
1532
1533 inst_iter--;
1534
1535 if (break_loop)
1536 break;
1537 }
1538}
1539
1540template <class Impl>
1541inline void
1542FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1543{
1544 if ((*instIt)->threadNumber == tid) {
1545 DPRINTF(O3CPU, "Squashing instruction, "
1546 "[tid:%i] [sn:%lli] PC %s\n",
1547 (*instIt)->threadNumber,
1548 (*instIt)->seqNum,
1549 (*instIt)->pcState());
1550
1551 // Mark it as squashed.
1552 (*instIt)->setSquashed();
1553
1554 // @todo: Formulate a consistent method for deleting
1555 // instructions from the instruction list
1556 // Remove the instruction from the list.
1557 removeList.push(instIt);
1558 }
1559}
1560
1561template <class Impl>
1562void
1563FullO3CPU<Impl>::cleanUpRemovedInsts()
1564{
1565 while (!removeList.empty()) {
1566 DPRINTF(O3CPU, "Removing instruction, "
1567 "[tid:%i] [sn:%lli] PC %s\n",
1568 (*removeList.front())->threadNumber,
1569 (*removeList.front())->seqNum,
1570 (*removeList.front())->pcState());
1571
1572 instList.erase(removeList.front());
1573
1574 removeList.pop();
1575 }
1576
1577 removeInstsThisCycle = false;
1578}
1579/*
1580template <class Impl>
1581void
1582FullO3CPU<Impl>::removeAllInsts()
1583{
1584 instList.clear();
1585}
1586*/
1587template <class Impl>
1588void
1589FullO3CPU<Impl>::dumpInsts()
1590{
1591 int num = 0;
1592
1593 ListIt inst_list_it = instList.begin();
1594
1595 cprintf("Dumping Instruction List\n");
1596
1597 while (inst_list_it != instList.end()) {
1598 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1599 "Squashed:%i\n\n",
1600 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1601 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1602 (*inst_list_it)->isSquashed());
1603 inst_list_it++;
1604 ++num;
1605 }
1606}
1607/*
1608template <class Impl>
1609void
1610FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1611{
1612 iew.wakeDependents(inst);
1613}
1614*/
1615template <class Impl>
1616void
1617FullO3CPU<Impl>::wakeCPU()
1618{
1619 if (activityRec.active() || tickEvent.scheduled()) {
1620 DPRINTF(Activity, "CPU already running.\n");
1621 return;
1622 }
1623
1624 DPRINTF(Activity, "Waking up CPU\n");
1625
1626 Cycles cycles(curCycle() - lastRunningCycle);
1627 // @todo: This is an oddity that is only here to match the stats
1628 if (cycles > 1) {
1629 --cycles;
1630 idleCycles += cycles;
1631 numCycles += cycles;
1632 ppCycles->notify(cycles);
1633 }
1634
1635 schedule(tickEvent, clockEdge());
1636}
1637
1638template <class Impl>
1639void
1640FullO3CPU<Impl>::wakeup(ThreadID tid)
1641{
1642 if (this->thread[tid]->status() != ThreadContext::Suspended)
1643 return;
1644
1645 this->wakeCPU();
1646
1647 DPRINTF(Quiesce, "Suspended Processor woken\n");
1648 this->threadContexts[tid]->activate();
1649}
1650
1651template <class Impl>
1652ThreadID
1653FullO3CPU<Impl>::getFreeTid()
1654{
1655 for (ThreadID tid = 0; tid < numThreads; tid++) {
1656 if (!tids[tid]) {
1657 tids[tid] = true;
1658 return tid;
1659 }
1660 }
1661
1662 return InvalidThreadID;
1663}
1664
1665template <class Impl>
1666void
1667FullO3CPU<Impl>::updateThreadPriority()
1668{
1669 if (activeThreads.size() > 1) {
1670 //DEFAULT TO ROUND ROBIN SCHEME
1671 //e.g. Move highest priority to end of thread list
1672 list<ThreadID>::iterator list_begin = activeThreads.begin();
1673
1674 unsigned high_thread = *list_begin;
1675
1676 activeThreads.erase(list_begin);
1677
1678 activeThreads.push_back(high_thread);
1679 }
1680}
1681
1682// Forward declaration of FullO3CPU.
1683template class FullO3CPU<O3CPUImpl>;