1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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82void
83BaseO3CPU::regStats()
84{
85 BaseCPU::regStats();
86}
87
88template<class Impl>
89bool
90FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
91{
92 DPRINTF(O3CPU, "Fetch unit received timing\n");
93 // We shouldn't ever get a block in ownership state
94 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
95 fetch->processCacheCompletion(pkt);
96
97 return true;
98}
99
100template<class Impl>
101void
102FullO3CPU<Impl>::IcachePort::recvRetry()
103{
104 fetch->recvRetry();
105}
106
107template <class Impl>
108bool
109FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
110{
111 return lsq->recvTimingResp(pkt);
112}
113
114template <class Impl>
115void
116FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
117{
118 lsq->recvTimingSnoopReq(pkt);
119}
120
121template <class Impl>
122void
123FullO3CPU<Impl>::DcachePort::recvRetry()
124{
125 lsq->recvRetry();
126}

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