1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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154 commit(this, params),
155
156 /* It is mandatory that all SMT threads use the same renaming mode as
157 * they are sharing registers and rename */
158 vecMode(RenameMode<TheISA::ISA>::init(params->isa[0])),
159 regFile(params->numPhysIntRegs,
160 params->numPhysFloatRegs,
161 params->numPhysVecRegs,
162 params->numPhysVecPredRegs,
163 params->numPhysCCRegs,
164 vecMode),
165
166 freeList(name() + ".freelist", &regFile),
167
168 rob(this, params),
169
170 scoreboard(name() + ".scoreboard",

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254 "or edit your workload size.");
255 }
256 }
257
258 //Make Sure That this a Valid Architeture
259 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
260 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
261 assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
262 assert(params->numPhysVecPredRegs >= numThreads * TheISA::NumVecPredRegs);
263 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
264
265 rename.setScoreboard(&scoreboard);
266 iew.setScoreboard(&scoreboard);
267
268 // Setup the rename map for whichever stages need it.
269 for (ThreadID tid = 0; tid < numThreads; tid++) {
270 isa[tid] = params->isa[tid];

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322 RegId lrid = RegId(VecElemClass, ridx, ldx);
323 PhysRegIdPtr phys_elem = freeList.getVecElem();
324 renameMap[tid].setEntry(lrid, phys_elem);
325 commitRenameMap[tid].setEntry(lrid, phys_elem);
326 }
327 }
328 }
329
330 for (RegIndex ridx = 0; ridx < TheISA::NumVecPredRegs; ++ridx) {
331 PhysRegIdPtr phys_reg = freeList.getVecPredReg();
332 renameMap[tid].setEntry(RegId(VecPredRegClass, ridx), phys_reg);
333 commitRenameMap[tid].setEntry(
334 RegId(VecPredRegClass, ridx), phys_reg);
335 }
336
337 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
338 PhysRegIdPtr phys_reg = freeList.getCCReg();
339 renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
340 commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
341 }
342 }
343
344 rename.setRenameMap(renameMap);

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542 .desc("number of vector regfile reads")
543 .prereq(vecRegfileReads);
544
545 vecRegfileWrites
546 .name(name() + ".vec_regfile_writes")
547 .desc("number of vector regfile writes")
548 .prereq(vecRegfileWrites);
549
550 vecPredRegfileReads
551 .name(name() + ".pred_regfile_reads")
552 .desc("number of predicate regfile reads")
553 .prereq(vecPredRegfileReads);
554
555 vecPredRegfileWrites
556 .name(name() + ".pred_regfile_writes")
557 .desc("number of predicate regfile writes")
558 .prereq(vecPredRegfileWrites);
559
560 ccRegfileReads
561 .name(name() + ".cc_regfile_reads")
562 .desc("number of cc regfile reads")
563 .prereq(ccRegfileReads);
564
565 ccRegfileWrites
566 .name(name() + ".cc_regfile_writes")
567 .desc("number of cc regfile writes")

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897 // Unbind Float Regs from Rename Map
898 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
899 reg_id.index()++) {
900 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
901 scoreboard.unsetReg(phys_reg);
902 freeList.addReg(phys_reg);
903 }
904
905 // Unbind Float Regs from Rename Map
906 for (unsigned preg = 0; preg < TheISA::NumVecPredRegs; preg++) {
907 PhysRegIdPtr phys_reg = renameMap[tid].lookup(
908 RegId(VecPredRegClass, preg));
909 scoreboard.unsetReg(phys_reg);
910 freeList.addReg(phys_reg);
911 }
912
913 // Unbind condition-code Regs from Rename Map
914 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
915 reg_id.index()++) {
916 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
917 scoreboard.unsetReg(phys_reg);
918 freeList.addReg(phys_reg);
919 }
920

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1356auto
1357FullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem&
1358{
1359 vecRegfileReads++;
1360 return regFile.readVecElem(phys_reg);
1361}
1362
1363template <class Impl>
1364auto
1365FullO3CPU<Impl>::readVecPredReg(PhysRegIdPtr phys_reg) const
1366 -> const VecPredRegContainer&
1367{
1368 vecPredRegfileReads++;
1369 return regFile.readVecPredReg(phys_reg);
1370}
1371
1372template <class Impl>
1373auto
1374FullO3CPU<Impl>::getWritableVecPredReg(PhysRegIdPtr phys_reg)
1375 -> VecPredRegContainer&
1376{
1377 vecPredRegfileWrites++;
1378 return regFile.getWritableVecPredReg(phys_reg);
1379}
1380
1381template <class Impl>
1382CCReg
1383FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1384{
1385 ccRegfileReads++;
1386 return regFile.readCCReg(phys_reg);
1387}
1388
1389template <class Impl>

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1415FullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val)
1416{
1417 vecRegfileWrites++;
1418 regFile.setVecElem(phys_reg, val);
1419}
1420
1421template <class Impl>
1422void
1423FullO3CPU<Impl>::setVecPredReg(PhysRegIdPtr phys_reg,
1424 const VecPredRegContainer& val)
1425{
1426 vecPredRegfileWrites++;
1427 regFile.setVecPredReg(phys_reg, val);
1428}
1429
1430template <class Impl>
1431void
1432FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1433{
1434 ccRegfileWrites++;
1435 regFile.setCCReg(phys_reg, val);
1436}
1437
1438template <class Impl>
1439RegVal

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1483 ThreadID tid) const -> const VecElem&
1484{
1485 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1486 RegId(VecElemClass, reg_idx, ldx));
1487 return readVecElem(phys_reg);
1488}
1489
1490template <class Impl>
1491auto
1492FullO3CPU<Impl>::readArchVecPredReg(int reg_idx, ThreadID tid) const
1493 -> const VecPredRegContainer&
1494{
1495 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1496 RegId(VecPredRegClass, reg_idx));
1497 return readVecPredReg(phys_reg);
1498}
1499
1500template <class Impl>
1501auto
1502FullO3CPU<Impl>::getWritableArchVecPredReg(int reg_idx, ThreadID tid)
1503 -> VecPredRegContainer&
1504{
1505 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1506 RegId(VecPredRegClass, reg_idx));
1507 return getWritableVecPredReg(phys_reg);
1508}
1509
1510template <class Impl>
1511CCReg
1512FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1513{
1514 ccRegfileReads++;
1515 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1516 RegId(CCRegClass, reg_idx));
1517
1518 return regFile.readCCReg(phys_reg);

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1557{
1558 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1559 RegId(VecElemClass, reg_idx, ldx));
1560 setVecElem(phys_reg, val);
1561}
1562
1563template <class Impl>
1564void
1565FullO3CPU<Impl>::setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
1566 ThreadID tid)
1567{
1568 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1569 RegId(VecPredRegClass, reg_idx));
1570 setVecPredReg(phys_reg, val);
1571}
1572
1573template <class Impl>
1574void
1575FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1576{
1577 ccRegfileWrites++;
1578 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1579 RegId(CCRegClass, reg_idx));
1580
1581 regFile.setCCReg(phys_reg, val);
1582}

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