1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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175 params->numPhysFloatRegs,
176 params->numPhysCCRegs),
177
178 freeList(name() + ".freelist", &regFile),
179
180 rob(this, params),
181
182 scoreboard(name() + ".scoreboard",
183 regFile.totalNumPhysRegs()),
184
185 isa(numThreads, NULL),
186
187 icachePort(&fetch, this),
188 dcachePort(&iew.ldstQueue, this),
189
190 timeBuffer(params->backComSize, params->forwardComSize),
191 fetchQueue(params->backComSize, params->forwardComSize),

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294 }
295
296 // Initialize rename map to assign physical registers to the
297 // architectural registers for active threads only.
298 for (ThreadID tid = 0; tid < active_threads; tid++) {
299 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
300 // Note that we can't use the rename() method because we don't
301 // want special treatment for the zero register at this point
302 PhysRegIdPtr phys_reg = freeList.getIntReg();
303 renameMap[tid].setIntEntry(ridx, phys_reg);
304 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
305 }
306
307 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
308 PhysRegIdPtr phys_reg = freeList.getFloatReg();
309 renameMap[tid].setFloatEntry(ridx, phys_reg);
310 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
311 }
312
313 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
314 PhysRegIdPtr phys_reg = freeList.getCCReg();
315 renameMap[tid].setCCEntry(ridx, phys_reg);
316 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
317 }
318 }
319
320 rename.setRenameMap(renameMap);
321 commit.setRenameMap(commitRenameMap);
322 rename.setFreeList(&freeList);

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785 src_tc = system->threadContexts[tid];
786 else
787 src_tc = tcBase(tid);
788
789 //Bind Int Regs to Rename Map
790
791 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
792 reg_id.regIdx++) {
793 PhysRegIdPtr phys_reg = freeList.getIntReg();
794 renameMap[tid].setEntry(reg_id, phys_reg);
795 scoreboard.setReg(phys_reg);
796 }
797
798 //Bind Float Regs to Rename Map
799 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
800 reg_id.regIdx++) {
801 PhysRegIdPtr phys_reg = freeList.getFloatReg();
802 renameMap[tid].setEntry(reg_id, phys_reg);
803 scoreboard.setReg(phys_reg);
804 }
805
806 //Bind condition-code Regs to Rename Map
807 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
808 reg_id.regIdx++) {
809 PhysRegIdPtr phys_reg = freeList.getCCReg();
810 renameMap[tid].setEntry(reg_id, phys_reg);
811 scoreboard.setReg(phys_reg);
812 }
813
814 //Copy Thread Data Into RegFile
815 //this->copyFromTC(tid);
816
817 //Set PC/NPC/NNPC

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839
840 // @todo: 2-27-2008: Fix how we free up rename mappings
841 // here to alleviate the case for double-freeing registers
842 // in SMT workloads.
843
844 // Unbind Int Regs from Rename Map
845 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
846 reg_id.regIdx++) {
847 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
848 scoreboard.unsetReg(phys_reg);
849 freeList.addReg(phys_reg);
850 }
851
852 // Unbind Float Regs from Rename Map
853 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
854 reg_id.regIdx++) {
855 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
856 scoreboard.unsetReg(phys_reg);
857 freeList.addReg(phys_reg);
858 }
859
860 // Unbind condition-code Regs from Rename Map
861 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
862 reg_id.regIdx++) {
863 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
864 scoreboard.unsetReg(phys_reg);
865 freeList.addReg(phys_reg);
866 }
867
868 // Squash Throughout Pipeline
869 DynInstPtr inst = commit.rob->readHeadInst(tid);
870 InstSeqNum squash_seq_num = inst->seqNum;
871 fetch.squash(0, squash_seq_num, inst, tid);

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1228 const TheISA::MiscReg &val, ThreadID tid)
1229{
1230 miscRegfileWrites++;
1231 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1232}
1233
1234template <class Impl>
1235uint64_t
1236FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
1237{
1238 intRegfileReads++;
1239 return regFile.readIntReg(phys_reg);
1240}
1241
1242template <class Impl>
1243FloatReg
1244FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg)
1245{
1246 fpRegfileReads++;
1247 return regFile.readFloatReg(phys_reg);
1248}
1249
1250template <class Impl>
1251FloatRegBits
1252FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
1253{
1254 fpRegfileReads++;
1255 return regFile.readFloatRegBits(phys_reg);
1256}
1257
1258template <class Impl>
1259CCReg
1260FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1261{
1262 ccRegfileReads++;
1263 return regFile.readCCReg(phys_reg);
1264}
1265
1266template <class Impl>
1267void
1268FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
1269{
1270 intRegfileWrites++;
1271 regFile.setIntReg(phys_reg, val);
1272}
1273
1274template <class Impl>
1275void
1276FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, FloatReg val)
1277{
1278 fpRegfileWrites++;
1279 regFile.setFloatReg(phys_reg, val);
1280}
1281
1282template <class Impl>
1283void
1284FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
1285{
1286 fpRegfileWrites++;
1287 regFile.setFloatRegBits(phys_reg, val);
1288}
1289
1290template <class Impl>
1291void
1292FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1293{
1294 ccRegfileWrites++;
1295 regFile.setCCReg(phys_reg, val);
1296}
1297
1298template <class Impl>
1299uint64_t
1300FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1301{
1302 intRegfileReads++;
1303 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1304
1305 return regFile.readIntReg(phys_reg);
1306}
1307
1308template <class Impl>
1309float
1310FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1311{
1312 fpRegfileReads++;
1313 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1314
1315 return regFile.readFloatReg(phys_reg);
1316}
1317
1318template <class Impl>
1319uint64_t
1320FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1321{
1322 fpRegfileReads++;
1323 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1324
1325 return regFile.readFloatRegBits(phys_reg);
1326}
1327
1328template <class Impl>
1329CCReg
1330FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1331{
1332 ccRegfileReads++;
1333 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1334
1335 return regFile.readCCReg(phys_reg);
1336}
1337
1338template <class Impl>
1339void
1340FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1341{
1342 intRegfileWrites++;
1343 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1344
1345 regFile.setIntReg(phys_reg, val);
1346}
1347
1348template <class Impl>
1349void
1350FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1351{
1352 fpRegfileWrites++;
1353 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1354
1355 regFile.setFloatReg(phys_reg, val);
1356}
1357
1358template <class Impl>
1359void
1360FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1361{
1362 fpRegfileWrites++;
1363 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1364
1365 regFile.setFloatRegBits(phys_reg, val);
1366}
1367
1368template <class Impl>
1369void
1370FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1371{
1372 ccRegfileWrites++;
1373 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1374
1375 regFile.setCCReg(phys_reg, val);
1376}
1377
1378template <class Impl>
1379TheISA::PCState
1380FullO3CPU<Impl>::pcState(ThreadID tid)
1381{

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