commit_impl.hh (9437:8088e94a9de0) commit_impl.hh (9444:ab47fe7f03f0)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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52#include "cpu/o3/commit.hh"
53#include "cpu/o3/thread_state.hh"
54#include "cpu/base.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "debug/Activity.hh"
58#include "debug/Commit.hh"
59#include "debug/CommitRate.hh"
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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52#include "cpu/o3/commit.hh"
53#include "cpu/o3/thread_state.hh"
54#include "cpu/base.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "debug/Activity.hh"
58#include "debug/Commit.hh"
59#include "debug/CommitRate.hh"
60#include "debug/Drain.hh"
60#include "debug/ExecFaulting.hh"
61#include "params/DerivO3CPU.hh"
62#include "sim/faults.hh"
63#include "sim/full_system.hh"
64
65using namespace std;
66
67template <class Impl>

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94 iewToCommitDelay(params->iewToCommitDelay),
95 commitToIEWDelay(params->commitToIEWDelay),
96 renameToROBDelay(params->renameToROBDelay),
97 fetchToCommitDelay(params->commitToFetchDelay),
98 renameWidth(params->renameWidth),
99 commitWidth(params->commitWidth),
100 numThreads(params->numThreads),
101 drainPending(false),
61#include "debug/ExecFaulting.hh"
62#include "params/DerivO3CPU.hh"
63#include "sim/faults.hh"
64#include "sim/full_system.hh"
65
66using namespace std;
67
68template <class Impl>

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95 iewToCommitDelay(params->iewToCommitDelay),
96 commitToIEWDelay(params->commitToIEWDelay),
97 renameToROBDelay(params->renameToROBDelay),
98 fetchToCommitDelay(params->commitToFetchDelay),
99 renameWidth(params->renameWidth),
100 commitWidth(params->commitWidth),
101 numThreads(params->numThreads),
102 drainPending(false),
102 switchedOut(false),
103 trapLatency(params->trapLatency),
104 canHandleInterrupts(true)
105{
106 _status = Active;
107 _nextStatus = Inactive;
108 std::string policy = params->smtCommitPolicy;
109
110 //Convert string to lowercase

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364 // Commit must broadcast the number of free entries it has at the
365 // start of the simulation, so it starts as active.
366 cpu->activateStage(O3CPU::CommitIdx);
367
368 cpu->activityThisCycle();
369}
370
371template <class Impl>
103 trapLatency(params->trapLatency),
104 canHandleInterrupts(true)
105{
106 _status = Active;
107 _nextStatus = Inactive;
108 std::string policy = params->smtCommitPolicy;
109
110 //Convert string to lowercase

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364 // Commit must broadcast the number of free entries it has at the
365 // start of the simulation, so it starts as active.
366 cpu->activateStage(O3CPU::CommitIdx);
367
368 cpu->activityThisCycle();
369}
370
371template <class Impl>
372bool
372void
373DefaultCommit<Impl>::drain()
374{
375 drainPending = true;
373DefaultCommit<Impl>::drain()
374{
375 drainPending = true;
376
377 return false;
378}
379
380template <class Impl>
381void
376}
377
378template <class Impl>
379void
382DefaultCommit<Impl>::switchOut()
380DefaultCommit<Impl>::drainResume()
383{
381{
384 switchedOut = true;
385 drainPending = false;
382 drainPending = false;
386 rob->switchOut();
387}
388
389template <class Impl>
390void
383}
384
385template <class Impl>
386void
391DefaultCommit<Impl>::resume()
387DefaultCommit<Impl>::drainSanityCheck() const
392{
388{
393 drainPending = false;
389 assert(isDrained());
390 rob->drainSanityCheck();
394}
395
396template <class Impl>
391}
392
393template <class Impl>
394bool
395DefaultCommit<Impl>::isDrained() const
396{
397 /* Make sure no one is executing microcode. There are two reasons
398 * for this:
399 * - Hardware virtualized CPUs can't switch into the middle of a
400 * microcode sequence.
401 * - The current fetch implementation will most likely get very
402 * confused if it tries to start fetching an instruction that
403 * is executing in the middle of a ucode sequence that changes
404 * address mappings. This can happen on for example x86.
405 */
406 for (ThreadID tid = 0; tid < numThreads; tid++) {
407 if (pc[tid].microPC() != 0)
408 return false;
409 }
410
411 /* Make sure that all instructions have finished committing before
412 * declaring the system as drained. We want the pipeline to be
413 * completely empty when we declare the CPU to be drained. This
414 * makes debugging easier since CPU handover and restoring from a
415 * checkpoint with a different CPU should have the same timing.
416 */
417 return rob->isEmpty() &&
418 interrupt == NoFault;
419}
420
421template <class Impl>
397void
398DefaultCommit<Impl>::takeOverFrom()
399{
422void
423DefaultCommit<Impl>::takeOverFrom()
424{
400 switchedOut = false;
401 _status = Active;
402 _nextStatus = Inactive;
403 for (ThreadID tid = 0; tid < numThreads; tid++) {
404 commitStatus[tid] = Idle;
405 changedROBNumEntries[tid] = false;
406 trapSquash[tid] = false;
407 tcSquash[tid] = false;
408 squashAfterInst[tid] = NULL;

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619
620template <class Impl>
621void
622DefaultCommit<Impl>::tick()
623{
624 wroteToTimeBuffer = false;
625 _nextStatus = Inactive;
626
425 _status = Active;
426 _nextStatus = Inactive;
427 for (ThreadID tid = 0; tid < numThreads; tid++) {
428 commitStatus[tid] = Idle;
429 changedROBNumEntries[tid] = false;
430 trapSquash[tid] = false;
431 tcSquash[tid] = false;
432 squashAfterInst[tid] = NULL;

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643
644template <class Impl>
645void
646DefaultCommit<Impl>::tick()
647{
648 wroteToTimeBuffer = false;
649 _nextStatus = Inactive;
650
627 if (drainPending && cpu->instList.empty() && !iewStage->hasStoresToWB() &&
628 interrupt == NoFault) {
629 cpu->signalDrained();
630 drainPending = false;
631 return;
632 }
633
634 if (activeThreads->empty())
635 return;
636
637 list<ThreadID>::iterator threads = activeThreads->begin();
638 list<ThreadID>::iterator end = activeThreads->end();
639
640 // Check if any of the threads are done squashing. Change the
641 // status if they are done.

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1013 // Keep track of the last sequence number commited
1014 lastCommitedSeqNum[tid] = head_inst->seqNum;
1015
1016 // If this is an instruction that doesn't play nicely with
1017 // others squash everything and restart fetch
1018 if (head_inst->isSquashAfter())
1019 squashAfter(tid, head_inst);
1020
651 if (activeThreads->empty())
652 return;
653
654 list<ThreadID>::iterator threads = activeThreads->begin();
655 list<ThreadID>::iterator end = activeThreads->end();
656
657 // Check if any of the threads are done squashing. Change the
658 // status if they are done.

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1030 // Keep track of the last sequence number commited
1031 lastCommitedSeqNum[tid] = head_inst->seqNum;
1032
1033 // If this is an instruction that doesn't play nicely with
1034 // others squash everything and restart fetch
1035 if (head_inst->isSquashAfter())
1036 squashAfter(tid, head_inst);
1037
1038 if (drainPending) {
1039 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1040 if (pc[tid].microPC() == 0 && interrupt == NoFault) {
1041 squashAfter(tid, head_inst);
1042 cpu->commitDrained(tid);
1043 }
1044 }
1045
1021 int count = 0;
1022 Addr oldpc;
1023 // Debug statement. Checks to make sure we're not
1024 // currently updating state while handling PC events.
1025 assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending);
1026 do {
1027 oldpc = pc[tid].instAddr();
1028 cpu->system->pcEventQueue.service(thread[tid]->getTC());

--- 468 unchanged lines hidden --- 		1046 int count = 0;
1047 Addr oldpc;
1048 // Debug statement. Checks to make sure we're not
1049 // currently updating state while handling PC events.
1050 assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending);
1051 do {
1052 oldpc = pc[tid].instAddr();
1053 cpu->system->pcEventQueue.service(thread[tid]->getTC());

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