commit_impl.hh (9427:ddf45c1d54d4) commit_impl.hh (9437:8088e94a9de0)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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139 changedROBNumEntries[tid] = false;
140 checkEmptyROB[tid] = false;
141 trapInFlight[tid] = false;
142 committedStores[tid] = false;
143 trapSquash[tid] = false;
144 tcSquash[tid] = false;
145 pc[tid].set(0);
146 lastCommitedSeqNum[tid] = 0;
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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139 changedROBNumEntries[tid] = false;
140 checkEmptyROB[tid] = false;
141 trapInFlight[tid] = false;
142 committedStores[tid] = false;
143 trapSquash[tid] = false;
144 tcSquash[tid] = false;
145 pc[tid].set(0);
146 lastCommitedSeqNum[tid] = 0;
147 squashAfterInst[tid] = NULL;
147 }
148 interrupt = NoFault;
149}
150
151template <class Impl>
152std::string
153DefaultCommit<Impl>::name() const
154{

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399 switchedOut = false;
400 _status = Active;
401 _nextStatus = Inactive;
402 for (ThreadID tid = 0; tid < numThreads; tid++) {
403 commitStatus[tid] = Idle;
404 changedROBNumEntries[tid] = false;
405 trapSquash[tid] = false;
406 tcSquash[tid] = false;
148 }
149 interrupt = NoFault;
150}
151
152template <class Impl>
153std::string
154DefaultCommit<Impl>::name() const
155{

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400 switchedOut = false;
401 _status = Active;
402 _nextStatus = Inactive;
403 for (ThreadID tid = 0; tid < numThreads; tid++) {
404 commitStatus[tid] = Idle;
405 changedROBNumEntries[tid] = false;
406 trapSquash[tid] = false;
407 tcSquash[tid] = false;
408 squashAfterInst[tid] = NULL;
407 }
408 squashCounter = 0;
409 rob->takeOverFrom();
410}
411
412template <class Impl>
413void
414DefaultCommit<Impl>::updateStatus()

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582 commitStatus[tid] = ROBSquashing;
583 cpu->activityThisCycle();
584
585 tcSquash[tid] = false;
586}
587
588template <class Impl>
589void
409 }
410 squashCounter = 0;
411 rob->takeOverFrom();
412}
413
414template <class Impl>
415void
416DefaultCommit<Impl>::updateStatus()

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584 commitStatus[tid] = ROBSquashing;
585 cpu->activityThisCycle();
586
587 tcSquash[tid] = false;
588}
589
590template <class Impl>
591void
590DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
591 uint64_t squash_after_seq_num)
592DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
592{
593{
593 youngestSeqNum[tid] = squash_after_seq_num;
594 DPRINTF(Commit, "Squashing after squash after request, "
595 "restarting at PC %s\n", pc[tid]);
594
596
595 rob->squash(squash_after_seq_num, tid);
596 changedROBNumEntries[tid] = true;
597 squashAll(tid);
598 // Make sure to inform the fetch stage of which instruction caused
599 // the squash. It'll try to re-fetch an instruction executing in
600 // microcode unless this is set.
601 toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
602 squashAfterInst[tid] = NULL;
597
603
598 // Send back the sequence number of the squashed instruction.
599 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
604 commitStatus[tid] = ROBSquashing;
605 cpu->activityThisCycle();
606}
600
607
601 toIEW->commitInfo[tid].squashInst = head_inst;
602 // Send back the squash signal to tell stages that they should squash.
603 toIEW->commitInfo[tid].squash = true;
604
605 // Send back the rob squashing signal so other stages know that
606 // the ROB is in the process of squashing.
607 toIEW->commitInfo[tid].robSquashing = true;
608
609 toIEW->commitInfo[tid].mispredictInst = NULL;
610
611 toIEW->commitInfo[tid].pc = pc[tid];
608template <class Impl>
609void
610DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst)
611{
612 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
612 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
613 tid, squash_after_seq_num);
614 commitStatus[tid] = ROBSquashing;
613 tid, head_inst->seqNum);
614
615 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
616 commitStatus[tid] = SquashAfterPending;
617 squashAfterInst[tid] = head_inst;
615}
616
617template <class Impl>
618void
619DefaultCommit<Impl>::tick()
620{
621 wroteToTimeBuffer = false;
622 _nextStatus = Inactive;

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792 // Not sure which one takes priority. I think if we have
793 // both, that's a bad sign.
794 if (trapSquash[tid] == true) {
795 assert(!tcSquash[tid]);
796 squashFromTrap(tid);
797 } else if (tcSquash[tid] == true) {
798 assert(commitStatus[tid] != TrapPending);
799 squashFromTC(tid);
618}
619
620template <class Impl>
621void
622DefaultCommit<Impl>::tick()
623{
624 wroteToTimeBuffer = false;
625 _nextStatus = Inactive;

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795 // Not sure which one takes priority. I think if we have
796 // both, that's a bad sign.
797 if (trapSquash[tid] == true) {
798 assert(!tcSquash[tid]);
799 squashFromTrap(tid);
800 } else if (tcSquash[tid] == true) {
801 assert(commitStatus[tid] != TrapPending);
802 squashFromTC(tid);
803 } else if (commitStatus[tid] == SquashAfterPending) {
804 // A squash from the previous cycle of the commit stage (i.e.,
805 // commitInsts() called squashAfter) is pending. Squash the
806 // thread now.
807 squashFromSquashAfter(tid);
800 }
801
802 // Squashed sequence number must be older than youngest valid
803 // instruction in the ROB. This prevents squashes from younger
804 // instructions overriding squashes from older instructions.
805 if (fromIEW->squash[tid] &&
806 commitStatus[tid] != TrapPending &&
807 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {

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1003 TheISA::advancePC(pc[tid], head_inst->staticInst);
1004
1005 // Keep track of the last sequence number commited
1006 lastCommitedSeqNum[tid] = head_inst->seqNum;
1007
1008 // If this is an instruction that doesn't play nicely with
1009 // others squash everything and restart fetch
1010 if (head_inst->isSquashAfter())
808 }
809
810 // Squashed sequence number must be older than youngest valid
811 // instruction in the ROB. This prevents squashes from younger
812 // instructions overriding squashes from older instructions.
813 if (fromIEW->squash[tid] &&
814 commitStatus[tid] != TrapPending &&
815 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {

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1011 TheISA::advancePC(pc[tid], head_inst->staticInst);
1012
1013 // Keep track of the last sequence number commited
1014 lastCommitedSeqNum[tid] = head_inst->seqNum;
1015
1016 // If this is an instruction that doesn't play nicely with
1017 // others squash everything and restart fetch
1018 if (head_inst->isSquashAfter())
1011 squashAfter(tid, head_inst, head_inst->seqNum);
1019 squashAfter(tid, head_inst);
1012
1013 int count = 0;
1014 Addr oldpc;
1015 // Debug statement. Checks to make sure we're not
1016 // currently updating state while handling PC events.
1017 assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending);
1018 do {
1019 oldpc = pc[tid].instAddr();

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1021 int count = 0;
1022 Addr oldpc;
1023 // Debug statement. Checks to make sure we're not
1024 // currently updating state while handling PC events.
1025 assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending);
1026 do {
1027 oldpc = pc[tid].instAddr();

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