commit_impl.hh (9252:f350fac86d0f) commit_impl.hh (9382:1c97b57d5169)
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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554void
555DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
556{
557 squashAll(tid);
558
559 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
560
561 thread[tid]->trapPending = false;
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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554void
555DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
556{
557 squashAll(tid);
558
559 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
560
561 thread[tid]->trapPending = false;
562 thread[tid]->inSyscall = false;
562 thread[tid]->noSquashFromTC = false;
563 trapInFlight[tid] = false;
564
565 trapSquash[tid] = false;
566
567 commitStatus[tid] = ROBSquashing;
568 cpu->activityThisCycle();
569}
570
571template <class Impl>
572void
573DefaultCommit<Impl>::squashFromTC(ThreadID tid)
574{
575 squashAll(tid);
576
577 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
578
563 trapInFlight[tid] = false;
564
565 trapSquash[tid] = false;
566
567 commitStatus[tid] = ROBSquashing;
568 cpu->activityThisCycle();
569}
570
571template <class Impl>
572void
573DefaultCommit<Impl>::squashFromTC(ThreadID tid)
574{
575 squashAll(tid);
576
577 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
578
579 thread[tid]->inSyscall = false;
579 thread[tid]->noSquashFromTC = false;
580 assert(!thread[tid]->trapPending);
581
582 commitStatus[tid] = ROBSquashing;
583 cpu->activityThisCycle();
584
585 tcSquash[tid] = false;
586}
587

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716 if (canHandleInterrupts && cpu->instList.empty()) {
717 // Squash or record that I need to squash this cycle if
718 // an interrupt needed to be handled.
719 DPRINTF(Commit, "Interrupt detected.\n");
720
721 // Clear the interrupt now that it's going to be handled
722 toIEW->commitInfo[0].clearInterrupt = true;
723
580 assert(!thread[tid]->trapPending);
581
582 commitStatus[tid] = ROBSquashing;
583 cpu->activityThisCycle();
584
585 tcSquash[tid] = false;
586}
587

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716 if (canHandleInterrupts && cpu->instList.empty()) {
717 // Squash or record that I need to squash this cycle if
718 // an interrupt needed to be handled.
719 DPRINTF(Commit, "Interrupt detected.\n");
720
721 // Clear the interrupt now that it's going to be handled
722 toIEW->commitInfo[0].clearInterrupt = true;
723
724 assert(!thread[0]->inSyscall);
725 thread[0]->inSyscall = true;
724 assert(!thread[0]->noSquashFromTC);
725 thread[0]->noSquashFromTC = true;
726
727 if (cpu->checker) {
728 cpu->checker->handlePendingInt();
729 }
730
731 // CPU will handle interrupt.
732 cpu->processInterrupts(interrupt);
733
726
727 if (cpu->checker) {
728 cpu->checker->handlePendingInt();
729 }
730
731 // CPU will handle interrupt.
732 cpu->processInterrupts(interrupt);
733
734 thread[0]->inSyscall = false;
734 thread[0]->noSquashFromTC = false;
735
736 commitStatus[0] = TrapPending;
737
738 // Generate trap squash event.
739 generateTrapEvent(0);
740
741 interrupt = NoFault;
742 } else {

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1009 // others squash everything and restart fetch
1010 if (head_inst->isSquashAfter())
1011 squashAfter(tid, head_inst, head_inst->seqNum);
1012
1013 int count = 0;
1014 Addr oldpc;
1015 // Debug statement. Checks to make sure we're not
1016 // currently updating state while handling PC events.
735
736 commitStatus[0] = TrapPending;
737
738 // Generate trap squash event.
739 generateTrapEvent(0);
740
741 interrupt = NoFault;
742 } else {

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1009 // others squash everything and restart fetch
1010 if (head_inst->isSquashAfter())
1011 squashAfter(tid, head_inst, head_inst->seqNum);
1012
1013 int count = 0;
1014 Addr oldpc;
1015 // Debug statement. Checks to make sure we're not
1016 // currently updating state while handling PC events.
1017 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1017 assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending);
1018 do {
1019 oldpc = pc[tid].instAddr();
1020 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1021 count++;
1022 } while (oldpc != pc[tid].instAddr());
1023 if (count > 1) {
1024 DPRINTF(Commit,
1025 "PC skip function event, stopping commit\n");

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1135
1136 head_inst->setCompleted();
1137
1138 if (cpu->checker) {
1139 // Need to check the instruction before its fault is processed
1140 cpu->checker->verify(head_inst);
1141 }
1142
1018 do {
1019 oldpc = pc[tid].instAddr();
1020 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1021 count++;
1022 } while (oldpc != pc[tid].instAddr());
1023 if (count > 1) {
1024 DPRINTF(Commit,
1025 "PC skip function event, stopping commit\n");

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1135
1136 head_inst->setCompleted();
1137
1138 if (cpu->checker) {
1139 // Need to check the instruction before its fault is processed
1140 cpu->checker->verify(head_inst);
1141 }
1142
1143 assert(!thread[tid]->inSyscall);
1143 assert(!thread[tid]->noSquashFromTC);
1144
1145 // Mark that we're in state update mode so that the trap's
1146 // execution doesn't generate extra squashes.
1144
1145 // Mark that we're in state update mode so that the trap's
1146 // execution doesn't generate extra squashes.
1147 thread[tid]->inSyscall = true;
1147 thread[tid]->noSquashFromTC = true;
1148
1149 // Execute the trap. Although it's slightly unrealistic in
1150 // terms of timing (as it doesn't wait for the full timing of
1151 // the trap event to complete before updating state), it's
1152 // needed to update the state as soon as possible. This
1153 // prevents external agents from changing any specific state
1154 // that the trap need.
1155 cpu->trap(inst_fault, tid, head_inst->staticInst);
1156
1157 // Exit state update mode to avoid accidental updating.
1148
1149 // Execute the trap. Although it's slightly unrealistic in
1150 // terms of timing (as it doesn't wait for the full timing of
1151 // the trap event to complete before updating state), it's
1152 // needed to update the state as soon as possible. This
1153 // prevents external agents from changing any specific state
1154 // that the trap need.
1155 cpu->trap(inst_fault, tid, head_inst->staticInst);
1156
1157 // Exit state update mode to avoid accidental updating.
1158 thread[tid]->inSyscall = false;
1158 thread[tid]->noSquashFromTC = false;
1159
1160 commitStatus[tid] = TrapPending;
1161
1162 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1163 head_inst->seqNum);
1164 if (head_inst->traceData) {
1165 if (DTRACE(ExecFaulting)) {
1166 head_inst->traceData->setFetchSeq(head_inst->seqNum);

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1160 commitStatus[tid] = TrapPending;
1161
1162 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1163 head_inst->seqNum);
1164 if (head_inst->traceData) {
1165 if (DTRACE(ExecFaulting)) {
1166 head_inst->traceData->setFetchSeq(head_inst->seqNum);

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