commit_impl.hh (9218:7e9e34d4203b) commit_impl.hh (9252:f350fac86d0f)
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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53#include "cpu/o3/thread_state.hh"
54#include "cpu/base.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "debug/Activity.hh"
58#include "debug/Commit.hh"
59#include "debug/CommitRate.hh"
60#include "debug/ExecFaulting.hh"
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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53#include "cpu/o3/thread_state.hh"
54#include "cpu/base.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "debug/Activity.hh"
58#include "debug/Commit.hh"
59#include "debug/CommitRate.hh"
60#include "debug/ExecFaulting.hh"
61#include "debug/O3PipeView.hh"
62#include "params/DerivO3CPU.hh"
63#include "sim/faults.hh"
64#include "sim/full_system.hh"
65
66using namespace std;
67
68template <class Impl>
69DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,

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1214 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1215 head_inst->renamedDestRegIdx(i));
1216 }
1217
1218 // Finally clear the head ROB entry.
1219 rob->retireHead(tid);
1220
1221#if TRACING_ON
61#include "params/DerivO3CPU.hh"
62#include "sim/faults.hh"
63#include "sim/full_system.hh"
64
65using namespace std;
66
67template <class Impl>
68DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,

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1213 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1214 head_inst->renamedDestRegIdx(i));
1215 }
1216
1217 // Finally clear the head ROB entry.
1218 rob->retireHead(tid);
1219
1220#if TRACING_ON
1222 // Print info needed by the pipeline activity viewer.
1223 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
1224 head_inst->fetchTick,
1225 head_inst->instAddr(),
1226 head_inst->microPC(),
1227 head_inst->seqNum,
1228 head_inst->staticInst->disassemble(head_inst->instAddr()));
1229 DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->fetchTick + head_inst->decodeTick);
1230 DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->fetchTick + head_inst->renameTick);
1231 DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->fetchTick + head_inst->dispatchTick);
1232 DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->fetchTick + head_inst->issueTick);
1233 DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->fetchTick + head_inst->completeTick);
1234 DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick());
1221 head_inst->commitTick = curTick() - head_inst->fetchTick;
1235#endif
1236
1237 // If this was a store, record it for this cycle.
1238 if (head_inst->isStore())
1239 committedStores[tid] = true;
1240
1241 // Return true to indicate that we have committed an instruction.
1242 return true;

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1223
1224 // If this was a store, record it for this cycle.
1225 if (head_inst->isStore())
1226 committedStores[tid] = true;
1227
1228 // Return true to indicate that we have committed an instruction.
1229 return true;

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