commit_impl.hh (8733:64a7bf8fa56c) commit_impl.hh (8793:5f25086326ac)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
50#include "config/full_system.hh"
51#include "config/the_isa.hh"
52#include "config/use_checker.hh"
53#include "cpu/o3/commit.hh"
54#include "cpu/o3/thread_state.hh"
50#include "config/the_isa.hh"
51#include "config/use_checker.hh"
52#include "cpu/o3/commit.hh"
53#include "cpu/o3/thread_state.hh"
55#include "cpu/base.hh"
56#include "cpu/exetrace.hh"
57#include "cpu/timebuf.hh"
58#include "debug/Activity.hh"
59#include "debug/Commit.hh"
60#include "debug/CommitRate.hh"
61#include "debug/ExecFaulting.hh"
62#include "debug/O3PipeView.hh"
63#include "params/DerivO3CPU.hh"
64#include "sim/faults.hh"
54#include "cpu/exetrace.hh"
55#include "cpu/timebuf.hh"
56#include "debug/Activity.hh"
57#include "debug/Commit.hh"
58#include "debug/CommitRate.hh"
59#include "debug/ExecFaulting.hh"
60#include "debug/O3PipeView.hh"
61#include "params/DerivO3CPU.hh"
62#include "sim/faults.hh"
63#include "sim/full_system.hh"
65
66#if USE_CHECKER
67#include "cpu/checker/cpu.hh"
68#endif
69
70using namespace std;
71
72template <class Impl>

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144 checkEmptyROB[tid] = false;
145 trapInFlight[tid] = false;
146 committedStores[tid] = false;
147 trapSquash[tid] = false;
148 tcSquash[tid] = false;
149 pc[tid].set(0);
150 lastCommitedSeqNum[tid] = 0;
151 }
64
65#if USE_CHECKER
66#include "cpu/checker/cpu.hh"
67#endif
68
69using namespace std;
70
71template <class Impl>

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143 checkEmptyROB[tid] = false;
144 trapInFlight[tid] = false;
145 committedStores[tid] = false;
146 trapSquash[tid] = false;
147 tcSquash[tid] = false;
148 pc[tid].set(0);
149 lastCommitedSeqNum[tid] = 0;
150 }
152#if FULL_SYSTEM
153 interrupt = NoFault;
151 interrupt = NoFault;
154#endif
155}
156
157template <class Impl>
158std::string
159DefaultCommit<Impl>::name() const
160{
161 return cpu->name() + ".commit";
162}

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696 if (wroteToTimeBuffer) {
697 DPRINTF(Activity, "Activity This Cycle.\n");
698 cpu->activityThisCycle();
699 }
700
701 updateStatus();
702}
703
152}
153
154template <class Impl>
155std::string
156DefaultCommit<Impl>::name() const
157{
158 return cpu->name() + ".commit";
159}

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693 if (wroteToTimeBuffer) {
694 DPRINTF(Activity, "Activity This Cycle.\n");
695 cpu->activityThisCycle();
696 }
697
698 updateStatus();
699}
700
704#if FULL_SYSTEM
705template <class Impl>
706void
707DefaultCommit<Impl>::handleInterrupt()
708{
709 // Verify that we still have an interrupt to handle
710 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
711 DPRINTF(Commit, "Pending interrupt is cleared by master before "
712 "it got handled. Restart fetching from the orig path.\n");

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723 DPRINTF(Commit, "Interrupt detected.\n");
724
725 // Clear the interrupt now that it's going to be handled
726 toIEW->commitInfo[0].clearInterrupt = true;
727
728 assert(!thread[0]->inSyscall);
729 thread[0]->inSyscall = true;
730
701template <class Impl>
702void
703DefaultCommit<Impl>::handleInterrupt()
704{
705 // Verify that we still have an interrupt to handle
706 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
707 DPRINTF(Commit, "Pending interrupt is cleared by master before "
708 "it got handled. Restart fetching from the orig path.\n");

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719 DPRINTF(Commit, "Interrupt detected.\n");
720
721 // Clear the interrupt now that it's going to be handled
722 toIEW->commitInfo[0].clearInterrupt = true;
723
724 assert(!thread[0]->inSyscall);
725 thread[0]->inSyscall = true;
726
731#if USE_CHECKER
732 if (cpu->checker) {
733 cpu->checker->handlePendingInt();
734 }
735#endif
736
737 // CPU will handle interrupt.
738 cpu->processInterrupts(interrupt);
739
740 thread[0]->inSyscall = false;
741
742 commitStatus[0] = TrapPending;
743
744 // Generate trap squash event.

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768
769 // Tell fetch that there is an interrupt pending. This
770 // will make fetch wait until it sees a non PAL-mode PC,
771 // at which point it stops fetching instructions.
772 if (interrupt != NoFault)
773 toIEW->commitInfo[0].interruptPending = true;
774}
775
727 // CPU will handle interrupt.
728 cpu->processInterrupts(interrupt);
729
730 thread[0]->inSyscall = false;
731
732 commitStatus[0] = TrapPending;
733
734 // Generate trap squash event.

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758
759 // Tell fetch that there is an interrupt pending. This
760 // will make fetch wait until it sees a non PAL-mode PC,
761 // at which point it stops fetching instructions.
762 if (interrupt != NoFault)
763 toIEW->commitInfo[0].interruptPending = true;
764}
765
776#endif // FULL_SYSTEM
777
778template <class Impl>
779void
780DefaultCommit<Impl>::commit()
781{
766template <class Impl>
767void
768DefaultCommit<Impl>::commit()
769{
770 if (FullSystem) {
771 // Check for any interrupt that we've already squashed for and start
772 // processing it.
773 if (interrupt != NoFault)
774 handleInterrupt();
782
775
783#if FULL_SYSTEM
784 // Check for any interrupt that we've already squashed for and
785 // start processing it.
786 if (interrupt != NoFault)
787 handleInterrupt();
776 // Check if we have a interrupt and get read to handle it
777 if (cpu->checkInterrupts(cpu->tcBase(0)))
778 propagateInterrupt();
779 }
788
780
789 // Check if we have a interrupt and get read to handle it
790 if (cpu->checkInterrupts(cpu->tcBase(0)))
791 propagateInterrupt();
792#endif // FULL_SYSTEM
793
794 ////////////////////////////////////
795 // Check for any possible squashes, handle them first
796 ////////////////////////////////////
797 list<ThreadID>::iterator threads = activeThreads->begin();
798 list<ThreadID>::iterator end = activeThreads->end();
799
800 while (threads != end) {
801 ThreadID tid = *threads++;

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995 // prefetches towards the total commit count.
996 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
997 cpu->instDone(tid);
998 }
999
1000 // Updates misc. registers.
1001 head_inst->updateMiscRegs();
1002
781 ////////////////////////////////////
782 // Check for any possible squashes, handle them first
783 ////////////////////////////////////
784 list<ThreadID>::iterator threads = activeThreads->begin();
785 list<ThreadID>::iterator end = activeThreads->end();
786
787 while (threads != end) {
788 ThreadID tid = *threads++;

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982 // prefetches towards the total commit count.
983 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
984 cpu->instDone(tid);
985 }
986
987 // Updates misc. registers.
988 head_inst->updateMiscRegs();
989
1003 cpu->traceFunctions(pc[tid].instAddr());
1004
1005 TheISA::advancePC(pc[tid], head_inst->staticInst);
1006
1007 // Keep track of the last sequence number commited
1008 lastCommitedSeqNum[tid] = head_inst->seqNum;
1009
1010 // If this is an instruction that doesn't play nicely with
1011 // others squash everything and restart fetch
1012 if (head_inst->isSquashAfter())

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1135 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1136 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1137 return false;
1138 }
1139
1140 head_inst->setCompleted();
1141
1142#if USE_CHECKER
990 TheISA::advancePC(pc[tid], head_inst->staticInst);
991
992 // Keep track of the last sequence number commited
993 lastCommitedSeqNum[tid] = head_inst->seqNum;
994
995 // If this is an instruction that doesn't play nicely with
996 // others squash everything and restart fetch
997 if (head_inst->isSquashAfter())

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1120 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1121 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1122 return false;
1123 }
1124
1125 head_inst->setCompleted();
1126
1127#if USE_CHECKER
1143 if (cpu->checker) {
1144 // Need to check the instruction before its fault is processed
1128 if (cpu->checker && head_inst->isStore()) {
1145 cpu->checker->verify(head_inst);
1146 }
1147#endif
1148
1149 assert(!thread[tid]->inSyscall);
1150
1151 // Mark that we're in state update mode so that the trap's
1152 // execution doesn't generate extra squashes.

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1179
1180 // Generate trap squash event.
1181 generateTrapEvent(tid);
1182 return false;
1183 }
1184
1185 updateComInstStats(head_inst);
1186
1129 cpu->checker->verify(head_inst);
1130 }
1131#endif
1132
1133 assert(!thread[tid]->inSyscall);
1134
1135 // Mark that we're in state update mode so that the trap's
1136 // execution doesn't generate extra squashes.

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1163
1164 // Generate trap squash event.
1165 generateTrapEvent(tid);
1166 return false;
1167 }
1168
1169 updateComInstStats(head_inst);
1170
1187#if FULL_SYSTEM
1188 if (thread[tid]->profile) {
1189 thread[tid]->profilePC = head_inst->instAddr();
1190 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1191 head_inst->staticInst);
1171 if (FullSystem) {
1172 if (thread[tid]->profile) {
1173 thread[tid]->profilePC = head_inst->instAddr();
1174 ProfileNode *node = thread[tid]->profile->consume(
1175 thread[tid]->getTC(), head_inst->staticInst);
1192
1176
1193 if (node)
1194 thread[tid]->profileNode = node;
1195 }
1196 if (CPA::available()) {
1197 if (head_inst->isControl()) {
1198 ThreadContext *tc = thread[tid]->getTC();
1199 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1177 if (node)
1178 thread[tid]->profileNode = node;
1200 }
1179 }
1180 if (CPA::available()) {
1181 if (head_inst->isControl()) {
1182 ThreadContext *tc = thread[tid]->getTC();
1183 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1184 }
1185 }
1201 }
1186 }
1202#endif
1203 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1204 head_inst->seqNum, head_inst->pcState());
1205 if (head_inst->traceData) {
1206 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1207 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1208 head_inst->traceData->dump();
1209 delete head_inst->traceData;
1210 head_inst->traceData = NULL;

--- 295 unchanged lines hidden --- 		1187 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1188 head_inst->seqNum, head_inst->pcState());
1189 if (head_inst->traceData) {
1190 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1191 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1192 head_inst->traceData->dump();
1193 delete head_inst->traceData;
1194 head_inst->traceData = NULL;

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