commit_impl.hh (8662:d4548b381e87) commit_impl.hh (8733:64a7bf8fa56c)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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723 DPRINTF(Commit, "Interrupt detected.\n");
724
725 // Clear the interrupt now that it's going to be handled
726 toIEW->commitInfo[0].clearInterrupt = true;
727
728 assert(!thread[0]->inSyscall);
729 thread[0]->inSyscall = true;
730
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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723 DPRINTF(Commit, "Interrupt detected.\n");
724
725 // Clear the interrupt now that it's going to be handled
726 toIEW->commitInfo[0].clearInterrupt = true;
727
728 assert(!thread[0]->inSyscall);
729 thread[0]->inSyscall = true;
730
731#if USE_CHECKER
732 if (cpu->checker) {
733 cpu->checker->handlePendingInt();
734 }
735#endif
736
731 // CPU will handle interrupt.
732 cpu->processInterrupts(interrupt);
733
734 thread[0]->inSyscall = false;
735
736 commitStatus[0] = TrapPending;
737
738 // Generate trap squash event.

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770#endif // FULL_SYSTEM
771
772template <class Impl>
773void
774DefaultCommit<Impl>::commit()
775{
776
777#if FULL_SYSTEM
737 // CPU will handle interrupt.
738 cpu->processInterrupts(interrupt);
739
740 thread[0]->inSyscall = false;
741
742 commitStatus[0] = TrapPending;
743
744 // Generate trap squash event.

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776#endif // FULL_SYSTEM
777
778template <class Impl>
779void
780DefaultCommit<Impl>::commit()
781{
782
783#if FULL_SYSTEM
778 // Check for any interrupt that we've already squashed for and start processing it.
784 // Check for any interrupt that we've already squashed for and
785 // start processing it.
779 if (interrupt != NoFault)
780 handleInterrupt();
781
782 // Check if we have a interrupt and get read to handle it
783 if (cpu->checkInterrupts(cpu->tcBase(0)))
784 propagateInterrupt();
785#endif // FULL_SYSTEM
786

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1128 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1129 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1130 return false;
1131 }
1132
1133 head_inst->setCompleted();
1134
1135#if USE_CHECKER
786 if (interrupt != NoFault)
787 handleInterrupt();
788
789 // Check if we have a interrupt and get read to handle it
790 if (cpu->checkInterrupts(cpu->tcBase(0)))
791 propagateInterrupt();
792#endif // FULL_SYSTEM
793

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1135 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1136 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1137 return false;
1138 }
1139
1140 head_inst->setCompleted();
1141
1142#if USE_CHECKER
1136 if (cpu->checker && head_inst->isStore()) {
1143 if (cpu->checker) {
1144 // Need to check the instruction before its fault is processed
1137 cpu->checker->verify(head_inst);
1138 }
1139#endif
1140
1141 assert(!thread[tid]->inSyscall);
1142
1143 // Mark that we're in state update mode so that the trap's
1144 // execution doesn't generate extra squashes.

--- 353 unchanged lines hidden --- 		1145 cpu->checker->verify(head_inst);
1146 }
1147#endif
1148
1149 assert(!thread[tid]->inSyscall);
1150
1151 // Mark that we're in state update mode so that the trap's
1152 // execution doesn't generate extra squashes.

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