commit_impl.hh (8346:ce8b9a250021) commit_impl.hh (8471:18e560ba1539)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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53#include "cpu/o3/commit.hh"
54#include "cpu/o3/thread_state.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "debug/Activity.hh"
58#include "debug/Commit.hh"
59#include "debug/CommitRate.hh"
60#include "debug/ExecFaulting.hh"
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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53#include "cpu/o3/commit.hh"
54#include "cpu/o3/thread_state.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "debug/Activity.hh"
58#include "debug/Commit.hh"
59#include "debug/CommitRate.hh"
60#include "debug/ExecFaulting.hh"
61#include "debug/O3PipeView.hh"
61#include "params/DerivO3CPU.hh"
62#include "sim/faults.hh"
63
64#if USE_CHECKER
65#include "cpu/checker/cpu.hh"
66#endif
67
68using namespace std;

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1202 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1203 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1204 head_inst->renamedDestRegIdx(i));
1205 }
1206
1207 // Finally clear the head ROB entry.
1208 rob->retireHead(tid);
1209
62#include "params/DerivO3CPU.hh"
63#include "sim/faults.hh"
64
65#if USE_CHECKER
66#include "cpu/checker/cpu.hh"
67#endif
68
69using namespace std;

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1203 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1204 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1205 head_inst->renamedDestRegIdx(i));
1206 }
1207
1208 // Finally clear the head ROB entry.
1209 rob->retireHead(tid);
1210
1211#if TRACING_ON
1212 // Print info needed by the pipeline activity viewer.
1213 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
1214 head_inst->fetchTick,
1215 head_inst->instAddr(),
1216 head_inst->microPC(),
1217 head_inst->seqNum,
1218 head_inst->staticInst->disassemble(head_inst->instAddr()));
1219 DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick);
1220 DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick);
1221 DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick);
1222 DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick);
1223 DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick);
1224 DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick());
1225#endif
1226
1210 // If this was a store, record it for this cycle.
1211 if (head_inst->isStore())
1212 committedStores[tid] = true;
1213
1214 // Return true to indicate that we have committed an instruction.
1215 return true;
1216}
1217

--- 260 unchanged lines hidden --- 		1227 // If this was a store, record it for this cycle.
1228 if (head_inst->isStore())
1229 committedStores[tid] = true;
1230
1231 // Return true to indicate that we have committed an instruction.
1232 return true;
1233}
1234

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