commit_impl.hh (8068:749581c26e71) commit_impl.hh (8137:48371b9fb929)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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536 // Send back the squash signal to tell stages that they should
537 // squash.
538 toIEW->commitInfo[tid].squash = true;
539
540 // Send back the rob squashing signal so other stages know that
541 // the ROB is in the process of squashing.
542 toIEW->commitInfo[tid].robSquashing = true;
543
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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536 // Send back the squash signal to tell stages that they should
537 // squash.
538 toIEW->commitInfo[tid].squash = true;
539
540 // Send back the rob squashing signal so other stages know that
541 // the ROB is in the process of squashing.
542 toIEW->commitInfo[tid].robSquashing = true;
543
544 toIEW->commitInfo[tid].branchMispredict = false;
545 toIEW->commitInfo[tid].mispredictInst = NULL;
544 toIEW->commitInfo[tid].mispredictInst = NULL;
545 toIEW->commitInfo[tid].squashInst = NULL;
546
547 toIEW->commitInfo[tid].pc = pc[tid];
548}
549
550template <class Impl>
551void
552DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
553{

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579 commitStatus[tid] = ROBSquashing;
580 cpu->activityThisCycle();
581
582 tcSquash[tid] = false;
583}
584
585template <class Impl>
586void
546
547 toIEW->commitInfo[tid].pc = pc[tid];
548}
549
550template <class Impl>
551void
552DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
553{

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579 commitStatus[tid] = ROBSquashing;
580 cpu->activityThisCycle();
581
582 tcSquash[tid] = false;
583}
584
585template <class Impl>
586void
587DefaultCommit<Impl>::squashAfter(ThreadID tid, uint64_t squash_after_seq_num)
587DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
588 uint64_t squash_after_seq_num)
588{
589 youngestSeqNum[tid] = squash_after_seq_num;
590
591 rob->squash(squash_after_seq_num, tid);
592 changedROBNumEntries[tid] = true;
593
594 // Send back the sequence number of the squashed instruction.
595 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
596
589{
590 youngestSeqNum[tid] = squash_after_seq_num;
591
592 rob->squash(squash_after_seq_num, tid);
593 changedROBNumEntries[tid] = true;
594
595 // Send back the sequence number of the squashed instruction.
596 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
597
598 toIEW->commitInfo[tid].squashInst = head_inst;
597 // Send back the squash signal to tell stages that they should squash.
598 toIEW->commitInfo[tid].squash = true;
599
600 // Send back the rob squashing signal so other stages know that
601 // the ROB is in the process of squashing.
602 toIEW->commitInfo[tid].robSquashing = true;
603
599 // Send back the squash signal to tell stages that they should squash.
600 toIEW->commitInfo[tid].squash = true;
601
602 // Send back the rob squashing signal so other stages know that
603 // the ROB is in the process of squashing.
604 toIEW->commitInfo[tid].robSquashing = true;
605
604 toIEW->commitInfo[tid].branchMispredict = false;
606 toIEW->commitInfo[tid].mispredictInst = NULL;
605
606 toIEW->commitInfo[tid].pc = pc[tid];
607 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
608 tid, squash_after_seq_num);
609 commitStatus[tid] = ROBSquashing;
610}
611
612template <class Impl>

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796
797 // Squashed sequence number must be older than youngest valid
798 // instruction in the ROB. This prevents squashes from younger
799 // instructions overriding squashes from older instructions.
800 if (fromIEW->squash[tid] &&
801 commitStatus[tid] != TrapPending &&
802 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
803
607
608 toIEW->commitInfo[tid].pc = pc[tid];
609 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
610 tid, squash_after_seq_num);
611 commitStatus[tid] = ROBSquashing;
612}
613
614template <class Impl>

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798
799 // Squashed sequence number must be older than youngest valid
800 // instruction in the ROB. This prevents squashes from younger
801 // instructions overriding squashes from older instructions.
802 if (fromIEW->squash[tid] &&
803 commitStatus[tid] != TrapPending &&
804 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
805
804 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
806 if (fromIEW->mispredictInst[tid]) {
807 DPRINTF(Commit,
808 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
805 tid,
809 tid,
806 fromIEW->mispredPC[tid],
810 fromIEW->mispredictInst[tid]->instAddr(),
807 fromIEW->squashedSeqNum[tid]);
811 fromIEW->squashedSeqNum[tid]);
812 } else {
813 DPRINTF(Commit,
814 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
815 tid, fromIEW->squashedSeqNum[tid]);
816 }
808
809 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
810 tid,
811 fromIEW->pc[tid].nextInstAddr());
812
813 commitStatus[tid] = ROBSquashing;
814
815 // If we want to include the squashing instruction in the squash,

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830 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
831
832 toIEW->commitInfo[tid].squash = true;
833
834 // Send back the rob squashing signal so other stages know that
835 // the ROB is in the process of squashing.
836 toIEW->commitInfo[tid].robSquashing = true;
837
817
818 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
819 tid,
820 fromIEW->pc[tid].nextInstAddr());
821
822 commitStatus[tid] = ROBSquashing;
823
824 // If we want to include the squashing instruction in the squash,

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839 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
840
841 toIEW->commitInfo[tid].squash = true;
842
843 // Send back the rob squashing signal so other stages know that
844 // the ROB is in the process of squashing.
845 toIEW->commitInfo[tid].robSquashing = true;
846
838 toIEW->commitInfo[tid].branchMispredict =
839 fromIEW->branchMispredict[tid];
840 toIEW->commitInfo[tid].mispredictInst =
841 fromIEW->mispredictInst[tid];
842 toIEW->commitInfo[tid].branchTaken =
843 fromIEW->branchTaken[tid];
847 toIEW->commitInfo[tid].mispredictInst =
848 fromIEW->mispredictInst[tid];
849 toIEW->commitInfo[tid].branchTaken =
850 fromIEW->branchTaken[tid];
851 toIEW->commitInfo[tid].squashInst = NULL;
844
845 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
846
852
853 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
854
847 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
848
849 if (toIEW->commitInfo[tid].branchMispredict) {
855 if (toIEW->commitInfo[tid].mispredictInst) {
850 ++branchMispredicts;
851 }
852 }
853
854 }
855
856 setNextStatus();
857

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983 TheISA::advancePC(pc[tid], head_inst->staticInst);
984
985 // Keep track of the last sequence number commited
986 lastCommitedSeqNum[tid] = head_inst->seqNum;
987
988 // If this is an instruction that doesn't play nicely with
989 // others squash everything and restart fetch
990 if (head_inst->isSquashAfter())
856 ++branchMispredicts;
857 }
858 }
859
860 }
861
862 setNextStatus();
863

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989 TheISA::advancePC(pc[tid], head_inst->staticInst);
990
991 // Keep track of the last sequence number commited
992 lastCommitedSeqNum[tid] = head_inst->seqNum;
993
994 // If this is an instruction that doesn't play nicely with
995 // others squash everything and restart fetch
996 if (head_inst->isSquashAfter())
991 squashAfter(tid, head_inst->seqNum);
997 squashAfter(tid, head_inst, head_inst->seqNum);
992
993 int count = 0;
994 Addr oldpc;
995 // Debug statement. Checks to make sure we're not
996 // currently updating state while handling PC events.
997 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
998 do {
999 oldpc = pc[tid].instAddr();

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999 int count = 0;
1000 Addr oldpc;
1001 // Debug statement. Checks to make sure we're not
1002 // currently updating state while handling PC events.
1003 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1004 do {
1005 oldpc = pc[tid].instAddr();

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