commit_impl.hh (7684:ce48527a3edb) commit_impl.hh (7720:65d338a8dba4)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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123 for (ThreadID tid = 0; tid < numThreads; tid++) {
124 commitStatus[tid] = Idle;
125 changedROBNumEntries[tid] = false;
126 checkEmptyROB[tid] = false;
127 trapInFlight[tid] = false;
128 committedStores[tid] = false;
129 trapSquash[tid] = false;
130 tcSquash[tid] = false;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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123 for (ThreadID tid = 0; tid < numThreads; tid++) {
124 commitStatus[tid] = Idle;
125 changedROBNumEntries[tid] = false;
126 checkEmptyROB[tid] = false;
127 trapInFlight[tid] = false;
128 committedStores[tid] = false;
129 trapSquash[tid] = false;
130 tcSquash[tid] = false;
131 microPC[tid] = 0;
132 nextMicroPC[tid] = 0;
133 PC[tid] = 0;
134 nextPC[tid] = 0;
135 nextNPC[tid] = 0;
131 pc[tid].set(0);
136 }
137#if FULL_SYSTEM
138 interrupt = NoFault;
139#endif
140}
141
142template <class Impl>
143std::string

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508 toIEW->commitInfo[tid].squash = true;
509
510 // Send back the rob squashing signal so other stages know that
511 // the ROB is in the process of squashing.
512 toIEW->commitInfo[tid].robSquashing = true;
513
514 toIEW->commitInfo[tid].branchMispredict = false;
515
132 }
133#if FULL_SYSTEM
134 interrupt = NoFault;
135#endif
136}
137
138template <class Impl>
139std::string

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504 toIEW->commitInfo[tid].squash = true;
505
506 // Send back the rob squashing signal so other stages know that
507 // the ROB is in the process of squashing.
508 toIEW->commitInfo[tid].robSquashing = true;
509
510 toIEW->commitInfo[tid].branchMispredict = false;
511
516 toIEW->commitInfo[tid].nextPC = PC[tid];
517 toIEW->commitInfo[tid].nextNPC = nextPC[tid];
518 toIEW->commitInfo[tid].nextMicroPC = nextMicroPC[tid];
512 toIEW->commitInfo[tid].pc = pc[tid];
519}
520
521template <class Impl>
522void
523DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
524{
525 squashAll(tid);
526
513}
514
515template <class Impl>
516void
517DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
518{
519 squashAll(tid);
520
527 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
521 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
528
529 thread[tid]->trapPending = false;
530 thread[tid]->inSyscall = false;
531 trapInFlight[tid] = false;
532
533 trapSquash[tid] = false;
534
535 commitStatus[tid] = ROBSquashing;
536 cpu->activityThisCycle();
537}
538
539template <class Impl>
540void
541DefaultCommit<Impl>::squashFromTC(ThreadID tid)
542{
543 squashAll(tid);
544
522
523 thread[tid]->trapPending = false;
524 thread[tid]->inSyscall = false;
525 trapInFlight[tid] = false;
526
527 trapSquash[tid] = false;
528
529 commitStatus[tid] = ROBSquashing;
530 cpu->activityThisCycle();
531}
532
533template <class Impl>
534void
535DefaultCommit<Impl>::squashFromTC(ThreadID tid)
536{
537 squashAll(tid);
538
545 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
539 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
546
547 thread[tid]->inSyscall = false;
548 assert(!thread[tid]->trapPending);
549
550 commitStatus[tid] = ROBSquashing;
551 cpu->activityThisCycle();
552
553 tcSquash[tid] = false;

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606
607 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
608 // The ROB has more instructions it can commit. Its next status
609 // will be active.
610 _nextStatus = Active;
611
612 DynInstPtr inst = rob->readHeadInst(tid);
613
540
541 thread[tid]->inSyscall = false;
542 assert(!thread[tid]->trapPending);
543
544 commitStatus[tid] = ROBSquashing;
545 cpu->activityThisCycle();
546
547 tcSquash[tid] = false;

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600
601 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
602 // The ROB has more instructions it can commit. Its next status
603 // will be active.
604 _nextStatus = Active;
605
606 DynInstPtr inst = rob->readHeadInst(tid);
607
614 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
608 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
615 " ROB and ready to commit\n",
609 " ROB and ready to commit\n",
616 tid, inst->seqNum, inst->readPC());
610 tid, inst->seqNum, inst->pcState());
617
618 } else if (!rob->isEmpty(tid)) {
619 DynInstPtr inst = rob->readHeadInst(tid);
620
621 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
611
612 } else if (!rob->isEmpty(tid)) {
613 DynInstPtr inst = rob->readHeadInst(tid);
614
615 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
622 "%#x is head of ROB and not ready\n",
623 tid, inst->seqNum, inst->readPC());
616 "%s is head of ROB and not ready\n",
617 tid, inst->seqNum, inst->pcState());
624 }
625
626 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
627 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
628 }
629
630
631 if (wroteToTimeBuffer) {

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733
734 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
735 tid,
736 fromIEW->mispredPC[tid],
737 fromIEW->squashedSeqNum[tid]);
738
739 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
740 tid,
618 }
619
620 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
621 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
622 }
623
624
625 if (wroteToTimeBuffer) {

--- 101 unchanged lines hidden (view full) ---

727
728 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
729 tid,
730 fromIEW->mispredPC[tid],
731 fromIEW->squashedSeqNum[tid]);
732
733 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
734 tid,
741 fromIEW->nextPC[tid]);
735 fromIEW->pc[tid].nextInstAddr());
742
743 commitStatus[tid] = ROBSquashing;
744
745 // If we want to include the squashing instruction in the squash,
746 // then use one older sequence number.
747 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
748
749 if (fromIEW->includeSquashInst[tid] == true) {

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766 toIEW->commitInfo[tid].robSquashing = true;
767
768 toIEW->commitInfo[tid].branchMispredict =
769 fromIEW->branchMispredict[tid];
770
771 toIEW->commitInfo[tid].branchTaken =
772 fromIEW->branchTaken[tid];
773
736
737 commitStatus[tid] = ROBSquashing;
738
739 // If we want to include the squashing instruction in the squash,
740 // then use one older sequence number.
741 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
742
743 if (fromIEW->includeSquashInst[tid] == true) {

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760 toIEW->commitInfo[tid].robSquashing = true;
761
762 toIEW->commitInfo[tid].branchMispredict =
763 fromIEW->branchMispredict[tid];
764
765 toIEW->commitInfo[tid].branchTaken =
766 fromIEW->branchTaken[tid];
767
774 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
775 toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
776 toIEW->commitInfo[tid].nextMicroPC = fromIEW->nextMicroPC[tid];
768 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
777
778 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
779
780 if (toIEW->commitInfo[tid].branchMispredict) {
781 ++branchMispredicts;
782 }
783 }
784

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875
876 rob->retireHead(commit_thread);
877
878 ++commitSquashedInsts;
879
880 // Record that the number of ROB entries has changed.
881 changedROBNumEntries[tid] = true;
882 } else {
769
770 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
771
772 if (toIEW->commitInfo[tid].branchMispredict) {
773 ++branchMispredicts;
774 }
775 }
776

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867
868 rob->retireHead(commit_thread);
869
870 ++commitSquashedInsts;
871
872 // Record that the number of ROB entries has changed.
873 changedROBNumEntries[tid] = true;
874 } else {
883 PC[tid] = head_inst->readPC();
884 nextPC[tid] = head_inst->readNextPC();
885 nextNPC[tid] = head_inst->readNextNPC();
886 nextMicroPC[tid] = head_inst->readNextMicroPC();
875 pc[tid] = head_inst->pcState();
887
888 // Increment the total number of non-speculative instructions
889 // executed.
890 // Hack for now: it really shouldn't happen until after the
891 // commit is deemed to be successful, but this count is needed
892 // for syscalls.
893 thread[tid]->funcExeInst++;
894

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906 ++commitCommittedInsts;
907
908 // To match the old model, don't count nops and instruction
909 // prefetches towards the total commit count.
910 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
911 cpu->instDone(tid);
912 }
913
876
877 // Increment the total number of non-speculative instructions
878 // executed.
879 // Hack for now: it really shouldn't happen until after the
880 // commit is deemed to be successful, but this count is needed
881 // for syscalls.
882 thread[tid]->funcExeInst++;
883

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895 ++commitCommittedInsts;
896
897 // To match the old model, don't count nops and instruction
898 // prefetches towards the total commit count.
899 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
900 cpu->instDone(tid);
901 }
902
914 PC[tid] = nextPC[tid];
915 nextPC[tid] = nextNPC[tid];
916 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
917 microPC[tid] = nextMicroPC[tid];
918 nextMicroPC[tid] = microPC[tid] + 1;
903 TheISA::advancePC(pc[tid], head_inst->staticInst);
919
920 int count = 0;
921 Addr oldpc;
922 // Debug statement. Checks to make sure we're not
923 // currently updating state while handling PC events.
924 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
925 do {
904
905 int count = 0;
906 Addr oldpc;
907 // Debug statement. Checks to make sure we're not
908 // currently updating state while handling PC events.
909 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
910 do {
926 oldpc = PC[tid];
911 oldpc = pc[tid].instAddr();
927 cpu->system->pcEventQueue.service(thread[tid]->getTC());
928 count++;
912 cpu->system->pcEventQueue.service(thread[tid]->getTC());
913 count++;
929 } while (oldpc != PC[tid]);
914 } while (oldpc != pc[tid].instAddr());
930 if (count > 1) {
931 DPRINTF(Commit,
932 "PC skip function event, stopping commit\n");
933 break;
934 }
935 } else {
915 if (count > 1) {
916 DPRINTF(Commit,
917 "PC skip function event, stopping commit\n");
918 break;
919 }
920 } else {
936 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
921 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
937 "[tid:%i] [sn:%i].\n",
922 "[tid:%i] [sn:%i].\n",
938 head_inst->readPC(), tid ,head_inst->seqNum);
923 head_inst->pcState(), tid ,head_inst->seqNum);
939 break;
940 }
941 }
942 }
943
944 DPRINTF(CommitRate, "%i\n", num_committed);
945 numCommittedDist.sample(num_committed);
946

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965 thread[tid]->funcExeInst--;
966
967 if (head_inst->isNonSpeculative() ||
968 head_inst->isStoreConditional() ||
969 head_inst->isMemBarrier() ||
970 head_inst->isWriteBarrier()) {
971
972 DPRINTF(Commit, "Encountered a barrier or non-speculative "
924 break;
925 }
926 }
927 }
928
929 DPRINTF(CommitRate, "%i\n", num_committed);
930 numCommittedDist.sample(num_committed);
931

--- 18 unchanged lines hidden (view full) ---

950 thread[tid]->funcExeInst--;
951
952 if (head_inst->isNonSpeculative() ||
953 head_inst->isStoreConditional() ||
954 head_inst->isMemBarrier() ||
955 head_inst->isWriteBarrier()) {
956
957 DPRINTF(Commit, "Encountered a barrier or non-speculative "
973 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
974 head_inst->seqNum, head_inst->readPC());
958 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
959 head_inst->seqNum, head_inst->pcState());
975
976 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
977 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
978 return false;
979 }
980
981 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
982

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989 return false;
990 } else if (head_inst->isLoad()) {
991 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
992 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
993 return false;
994 }
995
996 assert(head_inst->uncacheable());
960
961 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
962 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
963 return false;
964 }
965
966 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
967

--- 6 unchanged lines hidden (view full) ---

974 return false;
975 } else if (head_inst->isLoad()) {
976 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
977 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
978 return false;
979 }
980
981 assert(head_inst->uncacheable());
997 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
998 head_inst->seqNum, head_inst->readPC());
982 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
983 head_inst->seqNum, head_inst->pcState());
999
1000 // Send back the non-speculative instruction's sequence
1001 // number. Tell the lsq to re-execute the load.
1002 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1003 toIEW->commitInfo[tid].uncached = true;
1004 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1005
1006 head_inst->clearCanCommit();

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1029 // Use checker prior to updating anything due to traps or PC
1030 // based events.
1031 if (cpu->checker) {
1032 cpu->checker->verify(head_inst);
1033 }
1034#endif
1035
1036 if (inst_fault != NoFault) {
984
985 // Send back the non-speculative instruction's sequence
986 // number. Tell the lsq to re-execute the load.
987 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
988 toIEW->commitInfo[tid].uncached = true;
989 toIEW->commitInfo[tid].uncachedLoad = head_inst;
990
991 head_inst->clearCanCommit();

--- 22 unchanged lines hidden (view full) ---

1014 // Use checker prior to updating anything due to traps or PC
1015 // based events.
1016 if (cpu->checker) {
1017 cpu->checker->verify(head_inst);
1018 }
1019#endif
1020
1021 if (inst_fault != NoFault) {
1037 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1038 head_inst->seqNum, head_inst->readPC());
1022 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1023 head_inst->seqNum, head_inst->pcState());
1039
1040 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1041 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1042 return false;
1043 }
1044
1045 head_inst->setCompleted();
1046

--- 29 unchanged lines hidden (view full) ---

1076 head_inst->traceData->dump();
1077 }
1078 delete head_inst->traceData;
1079 head_inst->traceData = NULL;
1080 }
1081
1082 // Generate trap squash event.
1083 generateTrapEvent(tid);
1024
1025 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1026 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1027 return false;
1028 }
1029
1030 head_inst->setCompleted();
1031

--- 29 unchanged lines hidden (view full) ---

1061 head_inst->traceData->dump();
1062 }
1063 delete head_inst->traceData;
1064 head_inst->traceData = NULL;
1065 }
1066
1067 // Generate trap squash event.
1068 generateTrapEvent(tid);
1084// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1085 return false;
1086 }
1087
1088 updateComInstStats(head_inst);
1089
1090#if FULL_SYSTEM
1091 if (thread[tid]->profile) {
1069 return false;
1070 }
1071
1072 updateComInstStats(head_inst);
1073
1074#if FULL_SYSTEM
1075 if (thread[tid]->profile) {
1092// bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1093// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1094 thread[tid]->profilePC = head_inst->readPC();
1076 thread[tid]->profilePC = head_inst->instAddr();
1095 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1096 head_inst->staticInst);
1097
1098 if (node)
1099 thread[tid]->profileNode = node;
1100 }
1101 if (CPA::available()) {
1102 if (head_inst->isControl()) {
1103 ThreadContext *tc = thread[tid]->getTC();
1077 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1078 head_inst->staticInst);
1079
1080 if (node)
1081 thread[tid]->profileNode = node;
1082 }
1083 if (CPA::available()) {
1084 if (head_inst->isControl()) {
1085 ThreadContext *tc = thread[tid]->getTC();
1104 CPA::cpa()->swAutoBegin(tc, head_inst->readNextPC());
1086 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1105 }
1106 }
1107#endif
1108
1109 if (head_inst->traceData) {
1110 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1111 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1112 head_inst->traceData->dump();

--- 36 unchanged lines hidden (view full) ---

1149 inst = fromRename->insts[inst_num];
1150 ThreadID tid = inst->threadNumber;
1151
1152 if (!inst->isSquashed() &&
1153 commitStatus[tid] != ROBSquashing &&
1154 commitStatus[tid] != TrapPending) {
1155 changedROBNumEntries[tid] = true;
1156
1087 }
1088 }
1089#endif
1090
1091 if (head_inst->traceData) {
1092 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1093 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1094 head_inst->traceData->dump();

--- 36 unchanged lines hidden (view full) ---

1131 inst = fromRename->insts[inst_num];
1132 ThreadID tid = inst->threadNumber;
1133
1134 if (!inst->isSquashed() &&
1135 commitStatus[tid] != ROBSquashing &&
1136 commitStatus[tid] != TrapPending) {
1137 changedROBNumEntries[tid] = true;
1138
1157 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1158 inst->readPC(), inst->seqNum, tid);
1139 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1140 inst->pcState(), inst->seqNum, tid);
1159
1160 rob->insertInst(inst);
1161
1162 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1163
1164 youngestSeqNum[tid] = inst->seqNum;
1165 } else {
1141
1142 rob->insertInst(inst);
1143
1144 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1145
1146 youngestSeqNum[tid] = inst->seqNum;
1147 } else {
1166 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1148 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1167 "squashed, skipping.\n",
1149 "squashed, skipping.\n",
1168 inst->readPC(), inst->seqNum, tid);
1150 inst->pcState(), inst->seqNum, tid);
1169 }
1170 }
1171}
1172
1173template <class Impl>
1174void
1175DefaultCommit<Impl>::skidInsert()
1176{
1177 DPRINTF(Commit, "Attempting to any instructions from rename into "
1178 "skidBuffer.\n");
1179
1180 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1181 DynInstPtr inst = fromRename->insts[inst_num];
1182
1183 if (!inst->isSquashed()) {
1151 }
1152 }
1153}
1154
1155template <class Impl>
1156void
1157DefaultCommit<Impl>::skidInsert()
1158{
1159 DPRINTF(Commit, "Attempting to any instructions from rename into "
1160 "skidBuffer.\n");
1161
1162 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1163 DynInstPtr inst = fromRename->insts[inst_num];
1164
1165 if (!inst->isSquashed()) {
1184 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1185 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1166 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1167 "skidBuffer.\n", inst->pcState(), inst->seqNum,
1186 inst->threadNumber);
1187 skidBuffer.push(inst);
1188 } else {
1168 inst->threadNumber);
1169 skidBuffer.push(inst);
1170 } else {
1189 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1171 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1190 "squashed, skipping.\n",
1172 "squashed, skipping.\n",
1191 inst->readPC(), inst->seqNum, inst->threadNumber);
1173 inst->pcState(), inst->seqNum, inst->threadNumber);
1192 }
1193 }
1194}
1195
1196template <class Impl>
1197void
1198DefaultCommit<Impl>::markCompletedInsts()
1199{
1200 // Grab completed insts out of the IEW instruction queue, and mark
1201 // instructions completed within the ROB.
1202 for (int inst_num = 0;
1203 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1204 ++inst_num)
1205 {
1206 if (!fromIEW->insts[inst_num]->isSquashed()) {
1174 }
1175 }
1176}
1177
1178template <class Impl>
1179void
1180DefaultCommit<Impl>::markCompletedInsts()
1181{
1182 // Grab completed insts out of the IEW instruction queue, and mark
1183 // instructions completed within the ROB.
1184 for (int inst_num = 0;
1185 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1186 ++inst_num)
1187 {
1188 if (!fromIEW->insts[inst_num]->isSquashed()) {
1207 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1189 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1208 "within ROB.\n",
1209 fromIEW->insts[inst_num]->threadNumber,
1190 "within ROB.\n",
1191 fromIEW->insts[inst_num]->threadNumber,
1210 fromIEW->insts[inst_num]->readPC(),
1192 fromIEW->insts[inst_num]->pcState(),
1211 fromIEW->insts[inst_num]->seqNum);
1212
1213 // Mark the instruction as ready to commit.
1214 fromIEW->insts[inst_num]->setCanCommit();
1215 }
1216 }
1217}
1218

--- 165 unchanged lines hidden --- 		1193 fromIEW->insts[inst_num]->seqNum);
1194
1195 // Mark the instruction as ready to commit.
1196 fromIEW->insts[inst_num]->setCanCommit();
1197 }
1198 }
1199}
1200

--- 165 unchanged lines hidden ---