commit_impl.hh (5529:9ae69b9cd7fd) commit_impl.hh (5557:03c186e416aa)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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809 // ROB is empty, b) there are no outstanding stores, c) IEW
810 // stage has received any information regarding stores that
811 // committed.
812 // c) is checked by making sure to not consider the ROB empty
813 // on the same cycle as when stores have been committed.
814 // @todo: Make this handle multi-cycle communication between
815 // commit and IEW.
816 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 800 unchanged lines hidden (view full) ---

809 // ROB is empty, b) there are no outstanding stores, c) IEW
810 // stage has received any information regarding stores that
811 // committed.
812 // c) is checked by making sure to not consider the ROB empty
813 // on the same cycle as when stores have been committed.
814 // @todo: Make this handle multi-cycle communication between
815 // commit and IEW.
816 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
817 !iewStage->hasStoresToWB() && !committedStores[tid]) {
817 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
818 checkEmptyROB[tid] = false;
819 toIEW->commitInfo[tid].usedROB = true;
820 toIEW->commitInfo[tid].emptyROB = true;
821 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
822 wroteToTimeBuffer = true;
823 }
824
825 }

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963 head_inst->isStoreConditional() ||
964 head_inst->isMemBarrier() ||
965 head_inst->isWriteBarrier()) {
966
967 DPRINTF(Commit, "Encountered a barrier or non-speculative "
968 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
969 head_inst->seqNum, head_inst->readPC());
970
818 checkEmptyROB[tid] = false;
819 toIEW->commitInfo[tid].usedROB = true;
820 toIEW->commitInfo[tid].emptyROB = true;
821 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
822 wroteToTimeBuffer = true;
823 }
824
825 }

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963 head_inst->isStoreConditional() ||
964 head_inst->isMemBarrier() ||
965 head_inst->isWriteBarrier()) {
966
967 DPRINTF(Commit, "Encountered a barrier or non-speculative "
968 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
969 head_inst->seqNum, head_inst->readPC());
970
971 if (inst_num > 0 || iewStage->hasStoresToWB()) {
971 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
972 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
973 return false;
974 }
975
976 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
977
978 // Change the instruction so it won't try to commit again until
979 // it is executed.
980 head_inst->clearCanCommit();
981
982 ++commitNonSpecStalls;
983
984 return false;
985 } else if (head_inst->isLoad()) {
972 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
973 return false;
974 }
975
976 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
977
978 // Change the instruction so it won't try to commit again until
979 // it is executed.
980 head_inst->clearCanCommit();
981
982 ++commitNonSpecStalls;
983
984 return false;
985 } else if (head_inst->isLoad()) {
986 if (inst_num > 0 || iewStage->hasStoresToWB()) {
986 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
987 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
988 return false;
989 }
990
991 assert(head_inst->uncacheable());
992 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
993 head_inst->seqNum, head_inst->readPC());
994

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1033 // possibly needing it for its fault.
1034 thread[tid]->setInst(
1035 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1036
1037 if (inst_fault != NoFault) {
1038 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1039 head_inst->seqNum, head_inst->readPC());
1040
987 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
988 return false;
989 }
990
991 assert(head_inst->uncacheable());
992 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
993 head_inst->seqNum, head_inst->readPC());
994

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1033 // possibly needing it for its fault.
1034 thread[tid]->setInst(
1035 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1036
1037 if (inst_fault != NoFault) {
1038 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1039 head_inst->seqNum, head_inst->readPC());
1040
1041 if (iewStage->hasStoresToWB() || inst_num > 0) {
1041 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1042 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1043 return false;
1044 }
1045
1046 head_inst->setCompleted();
1047
1048#if USE_CHECKER
1049 if (cpu->checker && head_inst->isStore()) {

--- 327 unchanged lines hidden --- 		1042 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1043 return false;
1044 }
1045
1046 head_inst->setCompleted();
1047
1048#if USE_CHECKER
1049 if (cpu->checker && head_inst->isStore()) {

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