commit_impl.hh (3867:807483cfab77) commit_impl.hh (3876:127c71cfe21a)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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983 head_inst->isStoreConditional() ||
984 head_inst->isMemBarrier() ||
985 head_inst->isWriteBarrier()) {
986
987 DPRINTF(Commit, "Encountered a barrier or non-speculative "
988 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
989 head_inst->seqNum, head_inst->readPC());
990
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 974 unchanged lines hidden (view full) ---

983 head_inst->isStoreConditional() ||
984 head_inst->isMemBarrier() ||
985 head_inst->isWriteBarrier()) {
986
987 DPRINTF(Commit, "Encountered a barrier or non-speculative "
988 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
989 head_inst->seqNum, head_inst->readPC());
990
991#if !FULL_SYSTEM
992 // Hack to make sure syscalls/memory barriers/quiesces
993 // aren't executed until all stores write back their data.
994 // This direct communication shouldn't be used for
995 // anything other than this.
991 // Hack to make sure syscalls/memory barriers/quiesces
992 // aren't executed until all stores write back their data.
993 // This direct communication shouldn't be used for
994 // anything other than this.
996 if (inst_num > 0 || iewStage->hasStoresToWB())
997#else
998 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
999 head_inst->isQuiesce()) &&
1000 iewStage->hasStoresToWB())
995 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
996 head_inst->isQuiesce()) &&
997 iewStage->hasStoresToWB())
1001#endif
1002 {
1003 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1004 return false;
998 {
999 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1000 return false;
1001 } else if (inst_num > 0) {
1002 DPRINTF(Commit, "Waiting to become head of commit.\n");
1003 return false;
1005 }
1006
1007 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1008
1009 // Change the instruction so it won't try to commit again until
1010 // it is executed.
1011 head_inst->clearCanCommit();
1012

--- 422 unchanged lines hidden --- 		1004 }
1005
1006 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1007
1008 // Change the instruction so it won't try to commit again until
1009 // it is executed.
1010 head_inst->clearCanCommit();
1011

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