commit_impl.hh (3791:f1783bae1afe) commit_impl.hh (3795:60ecc96c3cee)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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509
510 // Send back the rob squashing signal so other stages know that
511 // the ROB is in the process of squashing.
512 toIEW->commitInfo[tid].robSquashing = true;
513
514 toIEW->commitInfo[tid].branchMispredict = false;
515
516 toIEW->commitInfo[tid].nextPC = PC[tid];
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 500 unchanged lines hidden (view full) ---

509
510 // Send back the rob squashing signal so other stages know that
511 // the ROB is in the process of squashing.
512 toIEW->commitInfo[tid].robSquashing = true;
513
514 toIEW->commitInfo[tid].branchMispredict = false;
515
516 toIEW->commitInfo[tid].nextPC = PC[tid];
517 toIEW->commitInfo[tid].nextNPC = nextPC[tid];
517}
518
519template <class Impl>
520void
521DefaultCommit<Impl>::squashFromTrap(unsigned tid)
522{
523 squashAll(tid);
524

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765
766 toIEW->commitInfo[tid].branchMispredict =
767 fromIEW->branchMispredict[tid];
768
769 toIEW->commitInfo[tid].branchTaken =
770 fromIEW->branchTaken[tid];
771
772 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
518}
519
520template <class Impl>
521void
522DefaultCommit<Impl>::squashFromTrap(unsigned tid)
523{
524 squashAll(tid);
525

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766
767 toIEW->commitInfo[tid].branchMispredict =
768 fromIEW->branchMispredict[tid];
769
770 toIEW->commitInfo[tid].branchTaken =
771 fromIEW->branchTaken[tid];
772
773 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
774 toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
773
774 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
775
776 if (toIEW->commitInfo[tid].branchMispredict) {
777 ++branchMispredicts;
778 }
779 }
780

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776 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
777
778 if (toIEW->commitInfo[tid].branchMispredict) {
779 ++branchMispredicts;
780 }
781 }
782

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