commit_impl.hh (3708:b174ae14f007) commit_impl.hh (3771:808a4c19cf34)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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723
724 commitStatus[tid] = ROBSquashing;
725
726 // If we want to include the squashing instruction in the squash,
727 // then use one older sequence number.
728 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
729
730#if ISA_HAS_DELAY_SLOT
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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723
724 commitStatus[tid] = ROBSquashing;
725
726 // If we want to include the squashing instruction in the squash,
727 // then use one older sequence number.
728 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
729
730#if ISA_HAS_DELAY_SLOT
731 InstSeqNum bdelay_done_seq_num;
732 bool squash_bdelay_slot;
731 InstSeqNum bdelay_done_seq_num = squashed_inst;
732 bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
733
733
734 if (fromIEW->branchMispredict[tid]) {
735 if (fromIEW->branchTaken[tid] &&
736 fromIEW->condDelaySlotBranch[tid]) {
737 DPRINTF(Commit, "[tid:%i]: Cond. delay slot branch"
738 "mispredicted as taken. Squashing after previous "
739 "inst, [sn:%i]\n",
740 tid, squashed_inst);
741 bdelay_done_seq_num = squashed_inst;
742 squash_bdelay_slot = true;
743 } else {
744 DPRINTF(Commit, "[tid:%i]: Branch Mispredict. Squashing "
745 "after delay slot [sn:%i]\n", tid, squashed_inst+1);
746 bdelay_done_seq_num = squashed_inst + 1;
747 squash_bdelay_slot = false;
748 }
749 } else {
750 bdelay_done_seq_num = squashed_inst;
751 squash_bdelay_slot = true;
752 }
734 if (!squash_bdelay_slot)
735 bdelay_done_seq_num++;
736
753#endif
754
755 if (fromIEW->includeSquashInst[tid] == true) {
756 squashed_inst--;
757#if ISA_HAS_DELAY_SLOT
758 bdelay_done_seq_num--;
759#endif
760 }

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1112 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1113 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1114 head_inst->traceData->finalize();
1115 head_inst->traceData = NULL;
1116 }
1117
1118 // Update the commit rename map
1119 for (int i = 0; i < head_inst->numDestRegs(); i++) {
737#endif
738
739 if (fromIEW->includeSquashInst[tid] == true) {
740 squashed_inst--;
741#if ISA_HAS_DELAY_SLOT
742 bdelay_done_seq_num--;
743#endif
744 }

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1096 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1097 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1098 head_inst->traceData->finalize();
1099 head_inst->traceData = NULL;
1100 }
1101
1102 // Update the commit rename map
1103 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1120 renameMap[tid]->setEntry(head_inst->destRegIdx(i),
1104 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1121 head_inst->renamedDestRegIdx(i));
1122 }
1123
1124 if (head_inst->isCopy())
1125 panic("Should not commit any copy instructions!");
1126
1127 // Finally clear the head ROB entry.
1128 rob->retireHead(tid);

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1192#if ISA_HAS_DELAY_SLOT
1193 if (rename_idx < fromRename->size) {
1194 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1195
1196 for (;
1197 rename_idx < fromRename->size;
1198 rename_idx++) {
1199 DynInstPtr inst = fromRename->insts[rename_idx];
1105 head_inst->renamedDestRegIdx(i));
1106 }
1107
1108 if (head_inst->isCopy())
1109 panic("Should not commit any copy instructions!");
1110
1111 // Finally clear the head ROB entry.
1112 rob->retireHead(tid);

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1176#if ISA_HAS_DELAY_SLOT
1177 if (rename_idx < fromRename->size) {
1178 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1179
1180 for (;
1181 rename_idx < fromRename->size;
1182 rename_idx++) {
1183 DynInstPtr inst = fromRename->insts[rename_idx];
1184 int tid = inst->threadNumber;
1200
1201 if (!inst->isSquashed()) {
1202 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1185
1186 if (!inst->isSquashed()) {
1187 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1203 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1204 inst->threadNumber);
1188 "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
1205 skidBuffer.push(inst);
1206 } else {
1207 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1208 "squashed, skipping.\n",
1189 skidBuffer.push(inst);
1190 } else {
1191 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1192 "squashed, skipping.\n",
1209 inst->readPC(), inst->seqNum, inst->threadNumber);
1193 inst->readPC(), inst->seqNum, tid);
1210 }
1211 }
1212 }
1213#endif
1214
1215}
1216
1217template <class Impl>

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1195 }
1196 }
1197#endif
1198
1199}
1200
1201template <class Impl>

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