commit_impl.hh (3640:3a2f7b451641) commit_impl.hh (3698:0aa0884a9040)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 734 unchanged lines hidden (view full) ---

743 } else {
744 DPRINTF(Commit, "[tid:%i]: Branch Mispredict. Squashing "
745 "after delay slot [sn:%i]\n", tid, squashed_inst+1);
746 bdelay_done_seq_num = squashed_inst + 1;
747 squash_bdelay_slot = false;
748 }
749 } else {
750 bdelay_done_seq_num = squashed_inst;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 734 unchanged lines hidden (view full) ---

743 } else {
744 DPRINTF(Commit, "[tid:%i]: Branch Mispredict. Squashing "
745 "after delay slot [sn:%i]\n", tid, squashed_inst+1);
746 bdelay_done_seq_num = squashed_inst + 1;
747 squash_bdelay_slot = false;
748 }
749 } else {
750 bdelay_done_seq_num = squashed_inst;
751 squash_bdelay_slot = true;
751 }
752#endif
753
754 if (fromIEW->includeSquashInst[tid] == true) {
755 squashed_inst--;
756#if ISA_HAS_DELAY_SLOT
757 bdelay_done_seq_num--;
758#endif

--- 665 unchanged lines hidden --- 		752 }
753#endif
754
755 if (fromIEW->includeSquashInst[tid] == true) {
756 squashed_inst--;
757#if ISA_HAS_DELAY_SLOT
758 bdelay_done_seq_num--;
759#endif

--- 665 unchanged lines hidden ---