commit_impl.hh (3093:b09c33e66bce) commit_impl.hh (3125:febd811bccc6)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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1078
1079 // Exit state update mode to avoid accidental updating.
1080 thread[tid]->inSyscall = false;
1081
1082 commitStatus[tid] = TrapPending;
1083
1084 // Generate trap squash event.
1085 generateTrapEvent(tid);
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 1069 unchanged lines hidden (view full) ---

1078
1079 // Exit state update mode to avoid accidental updating.
1080 thread[tid]->inSyscall = false;
1081
1082 commitStatus[tid] = TrapPending;
1083
1084 // Generate trap squash event.
1085 generateTrapEvent(tid);
1086
1086// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1087 return false;
1088 }
1089
1090 updateComInstStats(head_inst);
1091
1087 return false;
1088 }
1089
1090 updateComInstStats(head_inst);
1091
1092#if FULL_SYSTEM
1093 if (thread[tid]->profile) {
1094// bool usermode =
1095// (cpu->readMiscReg(AlphaISA::IPR_DTB_CM, tid) & 0x18) != 0;
1096// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1097 thread[tid]->profilePC = head_inst->readPC();
1098 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getXCProxy(),
1099 head_inst->staticInst);
1100
1101 if (node)
1102 thread[tid]->profileNode = node;
1103 }
1104#endif
1105
1092 if (head_inst->traceData) {
1093 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1094 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1095 head_inst->traceData->finalize();
1096 head_inst->traceData = NULL;
1097 }
1098
1099 // Update the commit rename map
1100 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1101 renameMap[tid]->setEntry(head_inst->destRegIdx(i),
1102 head_inst->renamedDestRegIdx(i));
1103 }
1104
1106 if (head_inst->traceData) {
1107 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1108 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1109 head_inst->traceData->finalize();
1110 head_inst->traceData = NULL;
1111 }
1112
1113 // Update the commit rename map
1114 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1115 renameMap[tid]->setEntry(head_inst->destRegIdx(i),
1116 head_inst->renamedDestRegIdx(i));
1117 }
1118
1119 if (head_inst->isCopy())
1120 panic("Should not commit any copy instructions!");
1121
1105 // Finally clear the head ROB entry.
1106 rob->retireHead(tid);
1107
1108 // Return true to indicate that we have committed an instruction.
1109 return true;
1110}
1111
1112template <class Impl>

--- 290 unchanged lines hidden --- 		1122 // Finally clear the head ROB entry.
1123 rob->retireHead(tid);
1124
1125 // Return true to indicate that we have committed an instruction.
1126 return true;
1127}
1128
1129template <class Impl>

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