commit_impl.hh (2980:eab855f06b79) commit_impl.hh (3093:b09c33e66bce)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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717 fromIEW->nextPC[tid]);
718
719 commitStatus[tid] = ROBSquashing;
720
721 // If we want to include the squashing instruction in the squash,
722 // then use one older sequence number.
723 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
724
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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717 fromIEW->nextPC[tid]);
718
719 commitStatus[tid] = ROBSquashing;
720
721 // If we want to include the squashing instruction in the squash,
722 // then use one older sequence number.
723 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
724
725#if THE_ISA != ALPHA_ISA
725#if ISA_HAS_DELAY_SLOT
726 InstSeqNum bdelay_done_seq_num;
727 bool squash_bdelay_slot;
728
729 if (fromIEW->branchMispredict[tid]) {
730 if (fromIEW->branchTaken[tid] &&
731 fromIEW->condDelaySlotBranch[tid]) {
732 DPRINTF(Commit, "[tid:%i]: Cond. delay slot branch"
733 "mispredicted as taken. Squashing after previous "

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743 }
744 } else {
745 bdelay_done_seq_num = squashed_inst;
746 }
747#endif
748
749 if (fromIEW->includeSquashInst[tid] == true) {
750 squashed_inst--;
726 InstSeqNum bdelay_done_seq_num;
727 bool squash_bdelay_slot;
728
729 if (fromIEW->branchMispredict[tid]) {
730 if (fromIEW->branchTaken[tid] &&
731 fromIEW->condDelaySlotBranch[tid]) {
732 DPRINTF(Commit, "[tid:%i]: Cond. delay slot branch"
733 "mispredicted as taken. Squashing after previous "

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743 }
744 } else {
745 bdelay_done_seq_num = squashed_inst;
746 }
747#endif
748
749 if (fromIEW->includeSquashInst[tid] == true) {
750 squashed_inst--;
751#if THE_ISA != ALPHA_ISA
751#if ISA_HAS_DELAY_SLOT
752 bdelay_done_seq_num--;
753#endif
754 }
755 // All younger instructions will be squashed. Set the sequence
756 // number as the youngest instruction in the ROB.
757 youngestSeqNum[tid] = squashed_inst;
758
752 bdelay_done_seq_num--;
753#endif
754 }
755 // All younger instructions will be squashed. Set the sequence
756 // number as the youngest instruction in the ROB.
757 youngestSeqNum[tid] = squashed_inst;
758
759#if THE_ISA == ALPHA_ISA
760 rob->squash(squashed_inst, tid);
761 toIEW->commitInfo[tid].squashDelaySlot = true;
762#else
759#if ISA_HAS_DELAY_SLOT
763 rob->squash(bdelay_done_seq_num, tid);
764 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
765 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
760 rob->squash(bdelay_done_seq_num, tid);
761 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
762 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
763#else
764 rob->squash(squashed_inst, tid);
765 toIEW->commitInfo[tid].squashDelaySlot = true;
766#endif
767 changedROBNumEntries[tid] = true;
768
769 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
770
771 toIEW->commitInfo[tid].squash = true;
772
773 // Send back the rob squashing signal so other stages know that

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795
796 if (squashCounter != numThreads) {
797 // If we're not currently squashing, then get instructions.
798 getInsts();
799
800 // Try to commit any instructions.
801 commitInsts();
802 } else {
766#endif
767 changedROBNumEntries[tid] = true;
768
769 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
770
771 toIEW->commitInfo[tid].squash = true;
772
773 // Send back the rob squashing signal so other stages know that

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795
796 if (squashCounter != numThreads) {
797 // If we're not currently squashing, then get instructions.
798 getInsts();
799
800 // Try to commit any instructions.
801 commitInsts();
802 } else {
803#if THE_ISA != ALPHA_ISA
803#if ISA_HAS_DELAY_SLOT
804 skidInsert();
805#endif
806 }
807
808 //Check for any activity
809 threads = (*activeThreads).begin();
810
811 while (threads != (*activeThreads).end()) {

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901
902 // To match the old model, don't count nops and instruction
903 // prefetches towards the total commit count.
904 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
905 cpu->instDone(tid);
906 }
907
908 PC[tid] = nextPC[tid];
804 skidInsert();
805#endif
806 }
807
808 //Check for any activity
809 threads = (*activeThreads).begin();
810
811 while (threads != (*activeThreads).end()) {

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901
902 // To match the old model, don't count nops and instruction
903 // prefetches towards the total commit count.
904 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
905 cpu->instDone(tid);
906 }
907
908 PC[tid] = nextPC[tid];
909#if THE_ISA == ALPHA_ISA
910 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
911#else
909#if ISA_HAS_DELAY_SLOT
912 nextPC[tid] = nextNPC[tid];
913 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
910 nextPC[tid] = nextNPC[tid];
911 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
912#else
913 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
914#endif
915
916#if FULL_SYSTEM
917 int count = 0;
918 Addr oldpc;
919 do {
920 // Debug statement. Checks to make sure we're not
921 // currently updating state while handling PC events.

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1110}
1111
1112template <class Impl>
1113void
1114DefaultCommit<Impl>::getInsts()
1115{
1116 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1117
914#endif
915
916#if FULL_SYSTEM
917 int count = 0;
918 Addr oldpc;
919 do {
920 // Debug statement. Checks to make sure we're not
921 // currently updating state while handling PC events.

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1110}
1111
1112template <class Impl>
1113void
1114DefaultCommit<Impl>::getInsts()
1115{
1116 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1117
1118#if THE_ISA == ALPHA_ISA
1118#if ISA_HAS_DELAY_SLOT
1119 // Read any renamed instructions and place them into the ROB.
1119 // Read any renamed instructions and place them into the ROB.
1120 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1121#else
1122 // Read any renamed instructions and place them into the ROB.
1123 int insts_to_process = std::min((int)renameWidth,
1124 (int)(fromRename->size + skidBuffer.size()));
1125 int rename_idx = 0;
1126
1127 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1128 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1129 skidBuffer.size());
1120 int insts_to_process = std::min((int)renameWidth,
1121 (int)(fromRename->size + skidBuffer.size()));
1122 int rename_idx = 0;
1123
1124 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1125 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1126 skidBuffer.size());
1127#else
1128 // Read any renamed instructions and place them into the ROB.
1129 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1130#endif
1131
1132
1133 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1134 DynInstPtr inst;
1135
1130#endif
1131
1132
1133 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1134 DynInstPtr inst;
1135
1136#if THE_ISA == ALPHA_ISA
1137 inst = fromRename->insts[inst_num];
1138#else
1136#if ISA_HAS_DELAY_SLOT
1139 // Get insts from skidBuffer or from Rename
1140 if (skidBuffer.size() > 0) {
1141 DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1142 inst = skidBuffer.front();
1143 skidBuffer.pop();
1144 } else {
1145 DPRINTF(Commit, "Grabbing rename inst.\n");
1146 inst = fromRename->insts[rename_idx++];
1147 }
1137 // Get insts from skidBuffer or from Rename
1138 if (skidBuffer.size() > 0) {
1139 DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1140 inst = skidBuffer.front();
1141 skidBuffer.pop();
1142 } else {
1143 DPRINTF(Commit, "Grabbing rename inst.\n");
1144 inst = fromRename->insts[rename_idx++];
1145 }
1146#else
1147 inst = fromRename->insts[inst_num];
1148#endif
1149 int tid = inst->threadNumber;
1150
1151 if (!inst->isSquashed() &&
1152 commitStatus[tid] != ROBSquashing) {
1153 changedROBNumEntries[tid] = true;
1154
1155 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",

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1162 youngestSeqNum[tid] = inst->seqNum;
1163 } else {
1164 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1165 "squashed, skipping.\n",
1166 inst->readPC(), inst->seqNum, tid);
1167 }
1168 }
1169
1148#endif
1149 int tid = inst->threadNumber;
1150
1151 if (!inst->isSquashed() &&
1152 commitStatus[tid] != ROBSquashing) {
1153 changedROBNumEntries[tid] = true;
1154
1155 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",

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1162 youngestSeqNum[tid] = inst->seqNum;
1163 } else {
1164 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1165 "squashed, skipping.\n",
1166 inst->readPC(), inst->seqNum, tid);
1167 }
1168 }
1169
1170#if THE_ISA != ALPHA_ISA
1170#if ISA_HAS_DELAY_SLOT
1171 if (rename_idx < fromRename->size) {
1172 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1173
1174 for (;
1175 rename_idx < fromRename->size;
1176 rename_idx++) {
1177 DynInstPtr inst = fromRename->insts[rename_idx];
1178 int tid = inst->threadNumber;

--- 224 unchanged lines hidden --- 		1171 if (rename_idx < fromRename->size) {
1172 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1173
1174 for (;
1175 rename_idx < fromRename->size;
1176 rename_idx++) {
1177 DynInstPtr inst = fromRename->insts[rename_idx];
1178 int tid = inst->threadNumber;

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