commit_impl.hh (2935:d1223a6c9156) commit_impl.hh (2965:82703e01285a)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
29 */
30
31#include "config/full_system.hh"
32#include "config/use_checker.hh"
33
34#include <algorithm>
35#include <string>
36

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795 setNextStatus();
796
797 if (squashCounter != numThreads) {
798 // If we're not currently squashing, then get instructions.
799 getInsts();
800
801 // Try to commit any instructions.
802 commitInsts();
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#include <algorithm>
36#include <string>
37

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796 setNextStatus();
797
798 if (squashCounter != numThreads) {
799 // If we're not currently squashing, then get instructions.
800 getInsts();
801
802 // Try to commit any instructions.
803 commitInsts();
804 } else {
805#if THE_ISA != ALPHA_ISA
806 skidInsert();
807#endif
803 }
804
805 //Check for any activity
806 threads = (*activeThreads).begin();
807
808 while (threads != (*activeThreads).end()) {
809 unsigned tid = *threads++;
810

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1107}
1108
1109template <class Impl>
1110void
1111DefaultCommit<Impl>::getInsts()
1112{
1113 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1114
808 }
809
810 //Check for any activity
811 threads = (*activeThreads).begin();
812
813 while (threads != (*activeThreads).end()) {
814 unsigned tid = *threads++;
815

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1112}
1113
1114template <class Impl>
1115void
1116DefaultCommit<Impl>::getInsts()
1117{
1118 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1119
1120#if THE_ISA == ALPHA_ISA
1115 // Read any renamed instructions and place them into the ROB.
1116 int insts_to_process = min((int)renameWidth, fromRename->size);
1121 // Read any renamed instructions and place them into the ROB.
1122 int insts_to_process = min((int)renameWidth, fromRename->size);
1123#else
1124 // Read any renamed instructions and place them into the ROB.
1125 int insts_to_process = min((int)renameWidth,
1126 (int)(fromRename->size + skidBuffer.size()));
1127 int rename_idx = 0;
1117
1128
1118 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num)
1119 {
1120 DynInstPtr inst = fromRename->insts[inst_num];
1129 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1130 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1131 skidBuffer.size());
1132#endif
1133
1134
1135 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1136 DynInstPtr inst;
1137
1138#if THE_ISA == ALPHA_ISA
1139 inst = fromRename->insts[inst_num];
1140#else
1141 // Get insts from skidBuffer or from Rename
1142 if (skidBuffer.size() > 0) {
1143 DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1144 inst = skidBuffer.front();
1145 skidBuffer.pop();
1146 } else {
1147 DPRINTF(Commit, "Grabbing rename inst.\n");
1148 inst = fromRename->insts[rename_idx++];
1149 }
1150#endif
1121 int tid = inst->threadNumber;
1122
1123 if (!inst->isSquashed() &&
1124 commitStatus[tid] != ROBSquashing) {
1125 changedROBNumEntries[tid] = true;
1126
1127 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1128 inst->readPC(), inst->seqNum, tid);

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1133
1134 youngestSeqNum[tid] = inst->seqNum;
1135 } else {
1136 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1137 "squashed, skipping.\n",
1138 inst->readPC(), inst->seqNum, tid);
1139 }
1140 }
1151 int tid = inst->threadNumber;
1152
1153 if (!inst->isSquashed() &&
1154 commitStatus[tid] != ROBSquashing) {
1155 changedROBNumEntries[tid] = true;
1156
1157 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1158 inst->readPC(), inst->seqNum, tid);

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1163
1164 youngestSeqNum[tid] = inst->seqNum;
1165 } else {
1166 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1167 "squashed, skipping.\n",
1168 inst->readPC(), inst->seqNum, tid);
1169 }
1170 }
1171
1172#if THE_ISA != ALPHA_ISA
1173 if (rename_idx < fromRename->size) {
1174 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1175
1176 for (;
1177 rename_idx < fromRename->size;
1178 rename_idx++) {
1179 DynInstPtr inst = fromRename->insts[rename_idx];
1180 int tid = inst->threadNumber;
1181
1182 if (!inst->isSquashed()) {
1183 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1184 "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
1185 skidBuffer.push(inst);
1186 } else {
1187 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1188 "squashed, skipping.\n",
1189 inst->readPC(), inst->seqNum, tid);
1190 }
1191 }
1192 }
1193#endif
1194
1141}
1142
1143template <class Impl>
1144void
1195}
1196
1197template <class Impl>
1198void
1199DefaultCommit<Impl>::skidInsert()
1200{
1201 DPRINTF(Commit, "Attempting to any instructions from rename into "
1202 "skidBuffer.\n");
1203
1204 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1205 DynInstPtr inst = fromRename->insts[inst_num];
1206 int tid = inst->threadNumber;
1207
1208 if (!inst->isSquashed()) {
1209 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1210 "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
1211 skidBuffer.push(inst);
1212 } else {
1213 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1214 "squashed, skipping.\n",
1215 inst->readPC(), inst->seqNum, tid);
1216 }
1217 }
1218}
1219
1220template <class Impl>
1221void
1145DefaultCommit<Impl>::markCompletedInsts()
1146{
1147 // Grab completed insts out of the IEW instruction queue, and mark
1148 // instructions completed within the ROB.
1149 for (int inst_num = 0;
1150 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1151 ++inst_num)
1152 {

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1223{
1224 // Grab completed insts out of the IEW instruction queue, and mark
1225 // instructions completed within the ROB.
1226 for (int inst_num = 0;
1227 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1228 ++inst_num)
1229 {

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