commit_impl.hh (2918:20cdaf201249) commit_impl.hh (2935:d1223a6c9156)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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115 "RoundRobin,OldestReady}");
116 }
117
118 for (int i=0; i < numThreads; i++) {
119 commitStatus[i] = Idle;
120 changedROBNumEntries[i] = false;
121 trapSquash[i] = false;
122 tcSquash[i] = false;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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115 "RoundRobin,OldestReady}");
116 }
117
118 for (int i=0; i < numThreads; i++) {
119 commitStatus[i] = Idle;
120 changedROBNumEntries[i] = false;
121 trapSquash[i] = false;
122 tcSquash[i] = false;
123 PC[i] = nextPC[i] = 0;
123 PC[i] = nextPC[i] = nextNPC[i] = 0;
124 }
125}
126
127template <class Impl>
128std::string
129DefaultCommit<Impl>::name() const
130{
131 return cpu->name() + ".commit";

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718 fromIEW->nextPC[tid]);
719
720 commitStatus[tid] = ROBSquashing;
721
722 // If we want to include the squashing instruction in the squash,
723 // then use one older sequence number.
724 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
725
124 }
125}
126
127template <class Impl>
128std::string
129DefaultCommit<Impl>::name() const
130{
131 return cpu->name() + ".commit";

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718 fromIEW->nextPC[tid]);
719
720 commitStatus[tid] = ROBSquashing;
721
722 // If we want to include the squashing instruction in the squash,
723 // then use one older sequence number.
724 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
725
726 if (fromIEW->includeSquashInst[tid] == true)
727 squashed_inst--;
726#if THE_ISA != ALPHA_ISA
727 InstSeqNum bdelay_done_seq_num;
728 bool squash_bdelay_slot;
728
729
730 if (fromIEW->branchMispredict[tid]) {
731 if (fromIEW->branchTaken[tid] &&
732 fromIEW->condDelaySlotBranch[tid]) {
733 DPRINTF(Commit, "[tid:%i]: Cond. delay slot branch"
734 "mispredicted as taken. Squashing after previous "
735 "inst, [sn:%i]\n",
736 tid, squashed_inst);
737 bdelay_done_seq_num = squashed_inst;
738 squash_bdelay_slot = true;
739 } else {
740 DPRINTF(Commit, "[tid:%i]: Branch Mispredict. Squashing "
741 "after delay slot [sn:%i]\n", tid, squashed_inst+1);
742 bdelay_done_seq_num = squashed_inst + 1;
743 squash_bdelay_slot = false;
744 }
745 } else {
746 bdelay_done_seq_num = squashed_inst;
747 }
748#endif
749
750 if (fromIEW->includeSquashInst[tid] == true) {
751 squashed_inst--;
752#if THE_ISA != ALPHA_ISA
753 bdelay_done_seq_num--;
754#endif
755 }
729 // All younger instructions will be squashed. Set the sequence
730 // number as the youngest instruction in the ROB.
731 youngestSeqNum[tid] = squashed_inst;
732
756 // All younger instructions will be squashed. Set the sequence
757 // number as the youngest instruction in the ROB.
758 youngestSeqNum[tid] = squashed_inst;
759
760#if THE_ISA == ALPHA_ISA
733 rob->squash(squashed_inst, tid);
761 rob->squash(squashed_inst, tid);
762 toIEW->commitInfo[tid].squashDelaySlot = true;
763#else
764 rob->squash(bdelay_done_seq_num, tid);
765 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
766 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
767#endif
734 changedROBNumEntries[tid] = true;
735
736 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
737
738 toIEW->commitInfo[tid].squash = true;
739
740 // Send back the rob squashing signal so other stages know that
741 // the ROB is in the process of squashing.

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835
836 ++commitSquashedInsts;
837
838 // Record that the number of ROB entries has changed.
839 changedROBNumEntries[tid] = true;
840 } else {
841 PC[tid] = head_inst->readPC();
842 nextPC[tid] = head_inst->readNextPC();
768 changedROBNumEntries[tid] = true;
769
770 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
771
772 toIEW->commitInfo[tid].squash = true;
773
774 // Send back the rob squashing signal so other stages know that
775 // the ROB is in the process of squashing.

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869
870 ++commitSquashedInsts;
871
872 // Record that the number of ROB entries has changed.
873 changedROBNumEntries[tid] = true;
874 } else {
875 PC[tid] = head_inst->readPC();
876 nextPC[tid] = head_inst->readNextPC();
877 nextNPC[tid] = head_inst->readNextNPC();
843
844 // Increment the total number of non-speculative instructions
845 // executed.
846 // Hack for now: it really shouldn't happen until after the
847 // commit is deemed to be successful, but this count is needed
848 // for syscalls.
849 thread[tid]->funcExeInst++;
850

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863
864 // To match the old model, don't count nops and instruction
865 // prefetches towards the total commit count.
866 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
867 cpu->instDone(tid);
868 }
869
870 PC[tid] = nextPC[tid];
878
879 // Increment the total number of non-speculative instructions
880 // executed.
881 // Hack for now: it really shouldn't happen until after the
882 // commit is deemed to be successful, but this count is needed
883 // for syscalls.
884 thread[tid]->funcExeInst++;
885

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898
899 // To match the old model, don't count nops and instruction
900 // prefetches towards the total commit count.
901 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
902 cpu->instDone(tid);
903 }
904
905 PC[tid] = nextPC[tid];
906#if THE_ISA == ALPHA_ISA
871 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
907 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
908#else
909 nextPC[tid] = nextNPC[tid];
910 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
911#endif
912
872#if FULL_SYSTEM
873 int count = 0;
874 Addr oldpc;
875 do {
876 // Debug statement. Checks to make sure we're not
877 // currently updating state while handling PC events.
878 if (count == 0)
879 assert(!thread[tid]->inSyscall &&

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1064 // Return true to indicate that we have committed an instruction.
1065 return true;
1066}
1067
1068template <class Impl>
1069void
1070DefaultCommit<Impl>::getInsts()
1071{
913#if FULL_SYSTEM
914 int count = 0;
915 Addr oldpc;
916 do {
917 // Debug statement. Checks to make sure we're not
918 // currently updating state while handling PC events.
919 if (count == 0)
920 assert(!thread[tid]->inSyscall &&

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1105 // Return true to indicate that we have committed an instruction.
1106 return true;
1107}
1108
1109template <class Impl>
1110void
1111DefaultCommit<Impl>::getInsts()
1112{
1113 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1114
1072 // Read any renamed instructions and place them into the ROB.
1073 int insts_to_process = min((int)renameWidth, fromRename->size);
1074
1075 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num)
1076 {
1077 DynInstPtr inst = fromRename->insts[inst_num];
1078 int tid = inst->threadNumber;
1079

--- 205 unchanged lines hidden --- 		1115 // Read any renamed instructions and place them into the ROB.
1116 int insts_to_process = min((int)renameWidth, fromRename->size);
1117
1118 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num)
1119 {
1120 DynInstPtr inst = fromRename->insts[inst_num];
1121 int tid = inst->threadNumber;
1122

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