commit_impl.hh (2886:2fdb9976b0a3) commit_impl.hh (2918:20cdaf201249)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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991 if (cpu->checker) {
992 cpu->checker->verify(head_inst);
993 }
994#endif
995
996 // Check if the instruction caused a fault. If so, trap.
997 Fault inst_fault = head_inst->getFault();
998
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 982 unchanged lines hidden (view full) ---

991 if (cpu->checker) {
992 cpu->checker->verify(head_inst);
993 }
994#endif
995
996 // Check if the instruction caused a fault. If so, trap.
997 Fault inst_fault = head_inst->getFault();
998
999 // DTB will sometimes need the machine instruction for when
1000 // faults happen. So we will set it here, prior to the DTB
1001 // possibly needing it for its fault.
1002 thread[tid]->setInst(
1003 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1004
999 if (inst_fault != NoFault) {
1000 head_inst->setCompleted();
1001 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1002 head_inst->seqNum, head_inst->readPC());
1003
1004 if (iewStage->hasStoresToWB() || inst_num > 0) {
1005 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1006 return false;

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1013#endif
1014
1015 assert(!thread[tid]->inSyscall);
1016
1017 // Mark that we're in state update mode so that the trap's
1018 // execution doesn't generate extra squashes.
1019 thread[tid]->inSyscall = true;
1020
1005 if (inst_fault != NoFault) {
1006 head_inst->setCompleted();
1007 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1008 head_inst->seqNum, head_inst->readPC());
1009
1010 if (iewStage->hasStoresToWB() || inst_num > 0) {
1011 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1012 return false;

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1019#endif
1020
1021 assert(!thread[tid]->inSyscall);
1022
1023 // Mark that we're in state update mode so that the trap's
1024 // execution doesn't generate extra squashes.
1025 thread[tid]->inSyscall = true;
1026
1021 // DTB will sometimes need the machine instruction for when
1022 // faults happen. So we will set it here, prior to the DTB
1023 // possibly needing it for its fault.
1024 thread[tid]->setInst(
1025 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1026
1027 // Execute the trap. Although it's slightly unrealistic in
1028 // terms of timing (as it doesn't wait for the full timing of
1029 // the trap event to complete before updating state), it's
1030 // needed to update the state as soon as possible. This
1031 // prevents external agents from changing any specific state
1032 // that the trap need.
1033 cpu->trap(inst_fault, tid);
1034

--- 250 unchanged lines hidden --- 		1027 // Execute the trap. Although it's slightly unrealistic in
1028 // terms of timing (as it doesn't wait for the full timing of
1029 // the trap event to complete before updating state), it's
1030 // needed to update the state as soon as possible. This
1031 // prevents external agents from changing any specific state
1032 // that the trap need.
1033 cpu->trap(inst_fault, tid);
1034

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