commit_impl.hh (2874:5389a28b80fb) | commit_impl.hh (2875:9b6f6b75b187) |
---|---|
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 66 unchanged lines hidden (view full) --- 75 : squashCounter(0), 76 iewToCommitDelay(params->iewToCommitDelay), 77 commitToIEWDelay(params->commitToIEWDelay), 78 renameToROBDelay(params->renameToROBDelay), 79 fetchToCommitDelay(params->commitToFetchDelay), 80 renameWidth(params->renameWidth), 81 commitWidth(params->commitWidth), 82 numThreads(params->numberOfThreads), | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 66 unchanged lines hidden (view full) --- 75 : squashCounter(0), 76 iewToCommitDelay(params->iewToCommitDelay), 77 commitToIEWDelay(params->commitToIEWDelay), 78 renameToROBDelay(params->renameToROBDelay), 79 fetchToCommitDelay(params->commitToFetchDelay), 80 renameWidth(params->renameWidth), 81 commitWidth(params->commitWidth), 82 numThreads(params->numberOfThreads), |
83 drainPending(false), | 83 switchPending(false), |
84 switchedOut(false), | 84 switchedOut(false), |
85 trapLatency(params->trapLatency) | 85 trapLatency(params->trapLatency), 86 fetchTrapLatency(params->fetchTrapLatency) |
86{ 87 _status = Active; 88 _nextStatus = Inactive; 89 string policy = params->smtCommitPolicy; 90 91 //Convert string to lowercase 92 std::transform(policy.begin(), policy.end(), policy.begin(), 93 (int(*)(int)) tolower); --- 23 unchanged lines hidden (view full) --- 117 118 for (int i=0; i < numThreads; i++) { 119 commitStatus[i] = Idle; 120 changedROBNumEntries[i] = false; 121 trapSquash[i] = false; 122 tcSquash[i] = false; 123 PC[i] = nextPC[i] = 0; 124 } | 87{ 88 _status = Active; 89 _nextStatus = Inactive; 90 string policy = params->smtCommitPolicy; 91 92 //Convert string to lowercase 93 std::transform(policy.begin(), policy.end(), policy.begin(), 94 (int(*)(int)) tolower); --- 23 unchanged lines hidden (view full) --- 118 119 for (int i=0; i < numThreads; i++) { 120 commitStatus[i] = Idle; 121 changedROBNumEntries[i] = false; 122 trapSquash[i] = false; 123 tcSquash[i] = false; 124 PC[i] = nextPC[i] = 0; 125 } |
126 127 fetchFaultTick = 0; 128 fetchTrapWait = 0; |
|
125} 126 127template <class Impl> 128std::string 129DefaultCommit<Impl>::name() const 130{ 131 return cpu->name() + ".commit"; 132} --- 93 unchanged lines hidden (view full) --- 226 DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 227 cpu = cpu_ptr; 228 229 // Commit must broadcast the number of free entries it has at the start of 230 // the simulation, so it starts as active. 231 cpu->activateStage(O3CPU::CommitIdx); 232 233 trapLatency = cpu->cycles(trapLatency); | 129} 130 131template <class Impl> 132std::string 133DefaultCommit<Impl>::name() const 134{ 135 return cpu->name() + ".commit"; 136} --- 93 unchanged lines hidden (view full) --- 230 DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 231 cpu = cpu_ptr; 232 233 // Commit must broadcast the number of free entries it has at the start of 234 // the simulation, so it starts as active. 235 cpu->activateStage(O3CPU::CommitIdx); 236 237 trapLatency = cpu->cycles(trapLatency); |
238 fetchTrapLatency = cpu->cycles(fetchTrapLatency); |
|
234} 235 236template <class Impl> 237void 238DefaultCommit<Impl>::setThreads(vector<Thread *> &threads) 239{ 240 thread = threads; 241} --- 42 unchanged lines hidden (view full) --- 284 iewQueue = iq_ptr; 285 286 // Setup wire to get instructions from IEW. 287 fromIEW = iewQueue->getWire(-iewToCommitDelay); 288} 289 290template <class Impl> 291void | 239} 240 241template <class Impl> 242void 243DefaultCommit<Impl>::setThreads(vector<Thread *> &threads) 244{ 245 thread = threads; 246} --- 42 unchanged lines hidden (view full) --- 289 iewQueue = iq_ptr; 290 291 // Setup wire to get instructions from IEW. 292 fromIEW = iewQueue->getWire(-iewToCommitDelay); 293} 294 295template <class Impl> 296void |
297DefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage) 298{ 299 fetchStage = fetch_stage; 300} 301 302template <class Impl> 303void |
|
292DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 293{ 294 iewStage = iew_stage; 295} 296 297template<class Impl> 298void 299DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr) --- 33 unchanged lines hidden (view full) --- 333 toIEW->commitInfo[i].usedROB = true; 334 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 335 } 336 337 cpu->activityThisCycle(); 338} 339 340template <class Impl> | 304DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 305{ 306 iewStage = iew_stage; 307} 308 309template<class Impl> 310void 311DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr) --- 33 unchanged lines hidden (view full) --- 345 toIEW->commitInfo[i].usedROB = true; 346 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 347 } 348 349 cpu->activityThisCycle(); 350} 351 352template <class Impl> |
341bool 342DefaultCommit<Impl>::drain() | 353void 354DefaultCommit<Impl>::switchOut() |
343{ | 355{ |
344 drainPending = true; 345 346 // If it's already drained, return true. 347 if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 348 cpu->signalDrained(); 349 return true; 350 } 351 352 return false; | 356 switchPending = true; |
353} 354 355template <class Impl> 356void | 357} 358 359template <class Impl> 360void |
357DefaultCommit<Impl>::switchOut() | 361DefaultCommit<Impl>::doSwitchOut() |
358{ 359 switchedOut = true; | 362{ 363 switchedOut = true; |
360 drainPending = false; | 364 switchPending = false; |
361 rob->switchOut(); 362} 363 364template <class Impl> 365void | 365 rob->switchOut(); 366} 367 368template <class Impl> 369void |
366DefaultCommit<Impl>::resume() 367{ 368 drainPending = false; 369} 370 371template <class Impl> 372void | |
373DefaultCommit<Impl>::takeOverFrom() 374{ 375 switchedOut = false; 376 _status = Active; 377 _nextStatus = Inactive; 378 for (int i=0; i < numThreads; i++) { 379 commitStatus[i] = Idle; 380 changedROBNumEntries[i] = false; --- 174 unchanged lines hidden (view full) --- 555 556template <class Impl> 557void 558DefaultCommit<Impl>::tick() 559{ 560 wroteToTimeBuffer = false; 561 _nextStatus = Inactive; 562 | 370DefaultCommit<Impl>::takeOverFrom() 371{ 372 switchedOut = false; 373 _status = Active; 374 _nextStatus = Inactive; 375 for (int i=0; i < numThreads; i++) { 376 commitStatus[i] = Idle; 377 changedROBNumEntries[i] = false; --- 174 unchanged lines hidden (view full) --- 552 553template <class Impl> 554void 555DefaultCommit<Impl>::tick() 556{ 557 wroteToTimeBuffer = false; 558 _nextStatus = Inactive; 559 |
563 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 564 cpu->signalDrained(); 565 drainPending = false; | 560 if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 561 cpu->signalSwitched(); |
566 return; 567 } 568 | 562 return; 563 } 564 |
565 if ((*activeThreads).size() <= 0) 566 return; 567 |
|
569 list<unsigned>::iterator threads = (*activeThreads).begin(); 570 571 // Check if any of the threads are done squashing. Change the 572 // status if they are done. 573 while (threads != (*activeThreads).end()) { 574 unsigned tid = *threads++; 575 576 if (commitStatus[tid] == ROBSquashing) { --- 705 unchanged lines hidden --- | 568 list<unsigned>::iterator threads = (*activeThreads).begin(); 569 570 // Check if any of the threads are done squashing. Change the 571 // status if they are done. 572 while (threads != (*activeThreads).end()) { 573 unsigned tid = *threads++; 574 575 if (commitStatus[tid] == ROBSquashing) { --- 705 unchanged lines hidden --- |