commit_impl.hh (2732:d2443ce353d2) commit_impl.hh (2733:e0eac8fc5774)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "config/full_system.hh"
32#include "config/use_checker.hh"
33
31#include <algorithm>
32#include <string>
33
34#include "base/loader/symtab.hh"
35#include "base/timebuf.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/commit.hh"

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214 commitEligibleSamples
215 .name(name() + ".COM:bw_lim_events")
216 .desc("number cycles where commit BW limit reached")
217 ;
218}
219
220template <class Impl>
221void
34#include <algorithm>
35#include <string>
36
37#include "base/loader/symtab.hh"
38#include "base/timebuf.hh"
39#include "cpu/checker/cpu.hh"
40#include "cpu/exetrace.hh"
41#include "cpu/o3/commit.hh"

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217 commitEligibleSamples
218 .name(name() + ".COM:bw_lim_events")
219 .desc("number cycles where commit BW limit reached")
220 ;
221}
222
223template <class Impl>
224void
222DefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr)
225DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
223{
224 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
225 cpu = cpu_ptr;
226
227 // Commit must broadcast the number of free entries it has at the start of
228 // the simulation, so it starts as active.
226{
227 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
228 cpu = cpu_ptr;
229
230 // Commit must broadcast the number of free entries it has at the start of
231 // the simulation, so it starts as active.
229 cpu->activateStage(FullCPU::CommitIdx);
232 cpu->activateStage(O3CPU::CommitIdx);
230
231 trapLatency = cpu->cycles(trapLatency);
232 fetchTrapLatency = cpu->cycles(fetchTrapLatency);
233}
234
235template <class Impl>
236void
237DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)

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390 if (commitStatus[tid] == TrapPending ||
391 commitStatus[tid] == FetchTrapPending) {
392 _nextStatus = Active;
393 }
394 }
395
396 if (_nextStatus == Inactive && _status == Active) {
397 DPRINTF(Activity, "Deactivating stage.\n");
233
234 trapLatency = cpu->cycles(trapLatency);
235 fetchTrapLatency = cpu->cycles(fetchTrapLatency);
236}
237
238template <class Impl>
239void
240DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)

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393 if (commitStatus[tid] == TrapPending ||
394 commitStatus[tid] == FetchTrapPending) {
395 _nextStatus = Active;
396 }
397 }
398
399 if (_nextStatus == Inactive && _status == Active) {
400 DPRINTF(Activity, "Deactivating stage.\n");
398 cpu->deactivateStage(FullCPU::CommitIdx);
401 cpu->deactivateStage(O3CPU::CommitIdx);
399 } else if (_nextStatus == Active && _status == Inactive) {
400 DPRINTF(Activity, "Activating stage.\n");
402 } else if (_nextStatus == Active && _status == Inactive) {
403 DPRINTF(Activity, "Activating stage.\n");
401 cpu->activateStage(FullCPU::CommitIdx);
404 cpu->activateStage(O3CPU::CommitIdx);
402 }
403
404 _status = _nextStatus;
405}
406
407template <class Impl>
408void
409DefaultCommit<Impl>::setNextStatus()

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967 panic("Thread sync instructions are not handled yet.\n");
968 }
969
970 // Stores mark themselves as completed.
971 if (!head_inst->isStore()) {
972 head_inst->setCompleted();
973 }
974
405 }
406
407 _status = _nextStatus;
408}
409
410template <class Impl>
411void
412DefaultCommit<Impl>::setNextStatus()

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970 panic("Thread sync instructions are not handled yet.\n");
971 }
972
973 // Stores mark themselves as completed.
974 if (!head_inst->isStore()) {
975 head_inst->setCompleted();
976 }
977
978#if USE_CHECKER
975 // Use checker prior to updating anything due to traps or PC
976 // based events.
977 if (cpu->checker) {
978 cpu->checker->verify(head_inst);
979 }
979 // Use checker prior to updating anything due to traps or PC
980 // based events.
981 if (cpu->checker) {
982 cpu->checker->verify(head_inst);
983 }
984#endif
980
981 // Check if the instruction caused a fault. If so, trap.
982 Fault inst_fault = head_inst->getFault();
983
984 if (inst_fault != NoFault) {
985 head_inst->setCompleted();
986#if FULL_SYSTEM
987 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
988 head_inst->seqNum, head_inst->readPC());
989
990 if (iewStage->hasStoresToWB() || inst_num > 0) {
991 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
992 return false;
993 }
994
985
986 // Check if the instruction caused a fault. If so, trap.
987 Fault inst_fault = head_inst->getFault();
988
989 if (inst_fault != NoFault) {
990 head_inst->setCompleted();
991#if FULL_SYSTEM
992 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
993 head_inst->seqNum, head_inst->readPC());
994
995 if (iewStage->hasStoresToWB() || inst_num > 0) {
996 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
997 return false;
998 }
999
1000#if USE_CHECKER
995 if (cpu->checker && head_inst->isStore()) {
996 cpu->checker->verify(head_inst);
997 }
1001 if (cpu->checker && head_inst->isStore()) {
1002 cpu->checker->verify(head_inst);
1003 }
1004#endif
998
999 assert(!thread[tid]->inSyscall);
1000
1001 // Mark that we're in state update mode so that the trap's
1002 // execution doesn't generate extra squashes.
1003 thread[tid]->inSyscall = true;
1004
1005 // DTB will sometimes need the machine instruction for when

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1006 assert(!thread[tid]->inSyscall);
1007
1008 // Mark that we're in state update mode so that the trap's
1009 // execution doesn't generate extra squashes.
1010 thread[tid]->inSyscall = true;
1011
1012 // DTB will sometimes need the machine instruction for when

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