commit_impl.hh (2678:1f86b91dc3bb) commit_impl.hh (2680:246e7104f744)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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110 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
111 "RoundRobin,OldestReady}");
112 }
113
114 for (int i=0; i < numThreads; i++) {
115 commitStatus[i] = Idle;
116 changedROBNumEntries[i] = false;
117 trapSquash[i] = false;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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110 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
111 "RoundRobin,OldestReady}");
112 }
113
114 for (int i=0; i < numThreads; i++) {
115 commitStatus[i] = Idle;
116 changedROBNumEntries[i] = false;
117 trapSquash[i] = false;
118 xcSquash[i] = false;
118 tcSquash[i] = false;
119 PC[i] = nextPC[i] = 0;
120 }
121
122 fetchFaultTick = 0;
123 fetchTrapWait = 0;
124}
125
126template <class Impl>

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379{
380 switchedOut = false;
381 _status = Active;
382 _nextStatus = Inactive;
383 for (int i=0; i < numThreads; i++) {
384 commitStatus[i] = Idle;
385 changedROBNumEntries[i] = false;
386 trapSquash[i] = false;
119 PC[i] = nextPC[i] = 0;
120 }
121
122 fetchFaultTick = 0;
123 fetchTrapWait = 0;
124}
125
126template <class Impl>

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379{
380 switchedOut = false;
381 _status = Active;
382 _nextStatus = Inactive;
383 for (int i=0; i < numThreads; i++) {
384 commitStatus[i] = Idle;
385 changedROBNumEntries[i] = false;
386 trapSquash[i] = false;
387 xcSquash[i] = false;
387 tcSquash[i] = false;
388 }
389 squashCounter = 0;
390 rob->takeOverFrom();
391}
392
393template <class Impl>
394void
395DefaultCommit<Impl>::updateStatus()

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477
478 trap->schedule(curTick + trapLatency);
479
480 thread[tid]->trapPending = true;
481}
482
483template <class Impl>
484void
388 }
389 squashCounter = 0;
390 rob->takeOverFrom();
391}
392
393template <class Impl>
394void
395DefaultCommit<Impl>::updateStatus()

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477
478 trap->schedule(curTick + trapLatency);
479
480 thread[tid]->trapPending = true;
481}
482
483template <class Impl>
484void
485DefaultCommit<Impl>::generateXCEvent(unsigned tid)
485DefaultCommit<Impl>::generateTCEvent(unsigned tid)
486{
486{
487 DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid);
487 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
488
488
489 xcSquash[tid] = true;
489 tcSquash[tid] = true;
490}
491
492template <class Impl>
493void
494DefaultCommit<Impl>::squashAll(unsigned tid)
495{
496 // If we want to include the squashing instruction in the squash,
497 // then use one older sequence number.

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540 commitStatus[tid] = ROBSquashing;
541 cpu->activityThisCycle();
542
543 ++squashCounter;
544}
545
546template <class Impl>
547void
490}
491
492template <class Impl>
493void
494DefaultCommit<Impl>::squashAll(unsigned tid)
495{
496 // If we want to include the squashing instruction in the squash,
497 // then use one older sequence number.

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540 commitStatus[tid] = ROBSquashing;
541 cpu->activityThisCycle();
542
543 ++squashCounter;
544}
545
546template <class Impl>
547void
548DefaultCommit<Impl>::squashFromXC(unsigned tid)
548DefaultCommit<Impl>::squashFromTC(unsigned tid)
549{
550 squashAll(tid);
551
549{
550 squashAll(tid);
551
552 DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]);
552 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
553
554 thread[tid]->inSyscall = false;
555 assert(!thread[tid]->trapPending);
556
557 commitStatus[tid] = ROBSquashing;
558 cpu->activityThisCycle();
559
553
554 thread[tid]->inSyscall = false;
555 assert(!thread[tid]->trapPending);
556
557 commitStatus[tid] = ROBSquashing;
558 cpu->activityThisCycle();
559
560 xcSquash[tid] = false;
560 tcSquash[tid] = false;
561
562 ++squashCounter;
563}
564
565template <class Impl>
566void
567DefaultCommit<Impl>::tick()
568{

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646#if FULL_SYSTEM
647 // Process interrupts if interrupts are enabled, not in PAL mode,
648 // and no other traps or external squashes are currently pending.
649 // @todo: Allow other threads to handle interrupts.
650 if (cpu->checkInterrupts &&
651 cpu->check_interrupts() &&
652 !cpu->inPalMode(readPC()) &&
653 !trapSquash[0] &&
561
562 ++squashCounter;
563}
564
565template <class Impl>
566void
567DefaultCommit<Impl>::tick()
568{

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646#if FULL_SYSTEM
647 // Process interrupts if interrupts are enabled, not in PAL mode,
648 // and no other traps or external squashes are currently pending.
649 // @todo: Allow other threads to handle interrupts.
650 if (cpu->checkInterrupts &&
651 cpu->check_interrupts() &&
652 !cpu->inPalMode(readPC()) &&
653 !trapSquash[0] &&
654 !xcSquash[0]) {
654 !tcSquash[0]) {
655 // Tell fetch that there is an interrupt pending. This will
656 // make fetch wait until it sees a non PAL-mode PC, at which
657 // point it stops fetching instructions.
658 toIEW->commitInfo[0].interruptPending = true;
659
660 // Wait until the ROB is empty and all stores have drained in
661 // order to enter the interrupt.
662 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {

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715 DPRINTF(Commit, "Clearing fault from fetch\n");
716 commitStatus[0] = Running;
717 }
718 }
719*/
720 // Not sure which one takes priority. I think if we have
721 // both, that's a bad sign.
722 if (trapSquash[tid] == true) {
655 // Tell fetch that there is an interrupt pending. This will
656 // make fetch wait until it sees a non PAL-mode PC, at which
657 // point it stops fetching instructions.
658 toIEW->commitInfo[0].interruptPending = true;
659
660 // Wait until the ROB is empty and all stores have drained in
661 // order to enter the interrupt.
662 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {

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715 DPRINTF(Commit, "Clearing fault from fetch\n");
716 commitStatus[0] = Running;
717 }
718 }
719*/
720 // Not sure which one takes priority. I think if we have
721 // both, that's a bad sign.
722 if (trapSquash[tid] == true) {
723 assert(!xcSquash[tid]);
723 assert(!tcSquash[tid]);
724 squashFromTrap(tid);
724 squashFromTrap(tid);
725 } else if (xcSquash[tid] == true) {
726 squashFromXC(tid);
725 } else if (tcSquash[tid] == true) {
726 squashFromTC(tid);
727 }
728
729 // Squashed sequence number must be older than youngest valid
730 // instruction in the ROB. This prevents squashes from younger
731 // instructions overriding squashes from older instructions.
732 if (fromIEW->squash[tid] &&
733 commitStatus[tid] != TrapPending &&
734 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {

--- 577 unchanged lines hidden --- 		727 }
728
729 // Squashed sequence number must be older than youngest valid
730 // instruction in the ROB. This prevents squashes from younger
731 // instructions overriding squashes from older instructions.
732 if (fromIEW->squash[tid] &&
733 commitStatus[tid] != TrapPending &&
734 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {

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