commit_impl.hh (2665:a124942bacb8) commit_impl.hh (2669:f2b336e89d2a)
1/*
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
27 */
28
29#include <algorithm>
30#include <string>
31
32#include "base/loader/symtab.hh"
31#include "base/timebuf.hh"
33#include "base/timebuf.hh"
32#include "cpu/o3/commit.hh"
34#include "cpu/checker/cpu.hh"
33#include "cpu/exetrace.hh"
35#include "cpu/exetrace.hh"
36#include "cpu/o3/commit.hh"
37#include "cpu/o3/thread_state.hh"
34
38
39using namespace std;
40
35template <class Impl>
41template <class Impl>
36SimpleCommit<Impl>::SimpleCommit(Params &params)
37 : dcacheInterface(params.dcacheInterface),
38 iewToCommitDelay(params.iewToCommitDelay),
39 renameToROBDelay(params.renameToROBDelay),
40 renameWidth(params.renameWidth),
41 iewWidth(params.executeWidth),
42 commitWidth(params.commitWidth)
42DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
43 unsigned _tid)
44 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
43{
45{
44 _status = Idle;
46 this->setFlags(Event::AutoDelete);
45}
46
47template <class Impl>
48void
47}
48
49template <class Impl>
50void
49SimpleCommit<Impl>::regStats()
51DefaultCommit<Impl>::TrapEvent::process()
50{
52{
53 // This will get reset by commit if it was switched out at the
54 // time of this event processing.
55 commit->trapSquash[tid] = true;
56}
57
58template <class Impl>
59const char *
60DefaultCommit<Impl>::TrapEvent::description()
61{
62 return "Trap event";
63}
64
65template <class Impl>
66DefaultCommit<Impl>::DefaultCommit(Params *params)
67 : squashCounter(0),
68 iewToCommitDelay(params->iewToCommitDelay),
69 commitToIEWDelay(params->commitToIEWDelay),
70 renameToROBDelay(params->renameToROBDelay),
71 fetchToCommitDelay(params->commitToFetchDelay),
72 renameWidth(params->renameWidth),
73 iewWidth(params->executeWidth),
74 commitWidth(params->commitWidth),
75 numThreads(params->numberOfThreads),
76 switchedOut(false),
77 trapLatency(params->trapLatency),
78 fetchTrapLatency(params->fetchTrapLatency)
79{
80 _status = Active;
81 _nextStatus = Inactive;
82 string policy = params->smtCommitPolicy;
83
84 //Convert string to lowercase
85 std::transform(policy.begin(), policy.end(), policy.begin(),
86 (int(*)(int)) tolower);
87
88 //Assign commit policy
89 if (policy == "aggressive"){
90 commitPolicy = Aggressive;
91
92 DPRINTF(Commit,"Commit Policy set to Aggressive.");
93 } else if (policy == "roundrobin"){
94 commitPolicy = RoundRobin;
95
96 //Set-Up Priority List
97 for (int tid=0; tid < numThreads; tid++) {
98 priority_list.push_back(tid);
99 }
100
101 DPRINTF(Commit,"Commit Policy set to Round Robin.");
102 } else if (policy == "oldestready"){
103 commitPolicy = OldestReady;
104
105 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
106 } else {
107 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
108 "RoundRobin,OldestReady}");
109 }
110
111 for (int i=0; i < numThreads; i++) {
112 commitStatus[i] = Idle;
113 changedROBNumEntries[i] = false;
114 trapSquash[i] = false;
115 xcSquash[i] = false;
116 }
117
118 fetchFaultTick = 0;
119 fetchTrapWait = 0;
120}
121
122template <class Impl>
123std::string
124DefaultCommit<Impl>::name() const
125{
126 return cpu->name() + ".commit";
127}
128
129template <class Impl>
130void
131DefaultCommit<Impl>::regStats()
132{
133 using namespace Stats;
51 commitCommittedInsts
52 .name(name() + ".commitCommittedInsts")
53 .desc("The number of committed instructions")
54 .prereq(commitCommittedInsts);
55 commitSquashedInsts
56 .name(name() + ".commitSquashedInsts")
57 .desc("The number of squashed insts skipped by commit")
58 .prereq(commitSquashedInsts);
59 commitSquashEvents
60 .name(name() + ".commitSquashEvents")
61 .desc("The number of times commit is told to squash")
62 .prereq(commitSquashEvents);
63 commitNonSpecStalls
64 .name(name() + ".commitNonSpecStalls")
65 .desc("The number of times commit has been forced to stall to "
66 "communicate backwards")
67 .prereq(commitNonSpecStalls);
134 commitCommittedInsts
135 .name(name() + ".commitCommittedInsts")
136 .desc("The number of committed instructions")
137 .prereq(commitCommittedInsts);
138 commitSquashedInsts
139 .name(name() + ".commitSquashedInsts")
140 .desc("The number of squashed insts skipped by commit")
141 .prereq(commitSquashedInsts);
142 commitSquashEvents
143 .name(name() + ".commitSquashEvents")
144 .desc("The number of times commit is told to squash")
145 .prereq(commitSquashEvents);
146 commitNonSpecStalls
147 .name(name() + ".commitNonSpecStalls")
148 .desc("The number of times commit has been forced to stall to "
149 "communicate backwards")
150 .prereq(commitNonSpecStalls);
68 commitCommittedBranches
69 .name(name() + ".commitCommittedBranches")
70 .desc("The number of committed branches")
71 .prereq(commitCommittedBranches);
72 commitCommittedLoads
73 .name(name() + ".commitCommittedLoads")
74 .desc("The number of committed loads")
75 .prereq(commitCommittedLoads);
76 commitCommittedMemRefs
77 .name(name() + ".commitCommittedMemRefs")
78 .desc("The number of committed memory references")
79 .prereq(commitCommittedMemRefs);
80 branchMispredicts
81 .name(name() + ".branchMispredicts")
82 .desc("The number of times a branch was mispredicted")
83 .prereq(branchMispredicts);
151 branchMispredicts
152 .name(name() + ".branchMispredicts")
153 .desc("The number of times a branch was mispredicted")
154 .prereq(branchMispredicts);
84 n_committed_dist
155 numCommittedDist
85 .init(0,commitWidth,1)
86 .name(name() + ".COM:committed_per_cycle")
87 .desc("Number of insts commited each cycle")
88 .flags(Stats::pdf)
89 ;
156 .init(0,commitWidth,1)
157 .name(name() + ".COM:committed_per_cycle")
158 .desc("Number of insts commited each cycle")
159 .flags(Stats::pdf)
160 ;
161
162 statComInst
163 .init(cpu->number_of_threads)
164 .name(name() + ".COM:count")
165 .desc("Number of instructions committed")
166 .flags(total)
167 ;
168
169 statComSwp
170 .init(cpu->number_of_threads)
171 .name(name() + ".COM:swp_count")
172 .desc("Number of s/w prefetches committed")
173 .flags(total)
174 ;
175
176 statComRefs
177 .init(cpu->number_of_threads)
178 .name(name() + ".COM:refs")
179 .desc("Number of memory references committed")
180 .flags(total)
181 ;
182
183 statComLoads
184 .init(cpu->number_of_threads)
185 .name(name() + ".COM:loads")
186 .desc("Number of loads committed")
187 .flags(total)
188 ;
189
190 statComMembars
191 .init(cpu->number_of_threads)
192 .name(name() + ".COM:membars")
193 .desc("Number of memory barriers committed")
194 .flags(total)
195 ;
196
197 statComBranches
198 .init(cpu->number_of_threads)
199 .name(name() + ".COM:branches")
200 .desc("Number of branches committed")
201 .flags(total)
202 ;
203
204 //
205 // Commit-Eligible instructions...
206 //
207 // -> The number of instructions eligible to commit in those
208 // cycles where we reached our commit BW limit (less the number
209 // actually committed)
210 //
211 // -> The average value is computed over ALL CYCLES... not just
212 // the BW limited cycles
213 //
214 // -> The standard deviation is computed only over cycles where
215 // we reached the BW limit
216 //
217 commitEligible
218 .init(cpu->number_of_threads)
219 .name(name() + ".COM:bw_limited")
220 .desc("number of insts not committed due to BW limits")
221 .flags(total)
222 ;
223
224 commitEligibleSamples
225 .name(name() + ".COM:bw_lim_events")
226 .desc("number cycles where commit BW limit reached")
227 ;
90}
91
92template <class Impl>
93void
228}
229
230template <class Impl>
231void
94SimpleCommit<Impl>::setCPU(FullCPU *cpu_ptr)
232DefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr)
95{
96 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
97 cpu = cpu_ptr;
233{
234 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
235 cpu = cpu_ptr;
236
237 // Commit must broadcast the number of free entries it has at the start of
238 // the simulation, so it starts as active.
239 cpu->activateStage(FullCPU::CommitIdx);
240
241 trapLatency = cpu->cycles(trapLatency);
242 fetchTrapLatency = cpu->cycles(fetchTrapLatency);
98}
99
100template <class Impl>
101void
243}
244
245template <class Impl>
246void
102SimpleCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
247DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)
103{
248{
249 thread = threads;
250}
251
252template <class Impl>
253void
254DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
255{
104 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
105 timeBuffer = tb_ptr;
106
107 // Setup wire to send information back to IEW.
108 toIEW = timeBuffer->getWire(0);
109
110 // Setup wire to read data from IEW (for the ROB).
111 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
112}
113
114template <class Impl>
115void
256 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
257 timeBuffer = tb_ptr;
258
259 // Setup wire to send information back to IEW.
260 toIEW = timeBuffer->getWire(0);
261
262 // Setup wire to read data from IEW (for the ROB).
263 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
264}
265
266template <class Impl>
267void
116SimpleCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
268DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
117{
269{
270 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
271 fetchQueue = fq_ptr;
272
273 // Setup wire to get instructions from rename (for the ROB).
274 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
275}
276
277template <class Impl>
278void
279DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
280{
118 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
119 renameQueue = rq_ptr;
120
121 // Setup wire to get instructions from rename (for the ROB).
122 fromRename = renameQueue->getWire(-renameToROBDelay);
123}
124
125template <class Impl>
126void
281 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
282 renameQueue = rq_ptr;
283
284 // Setup wire to get instructions from rename (for the ROB).
285 fromRename = renameQueue->getWire(-renameToROBDelay);
286}
287
288template <class Impl>
289void
127SimpleCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
290DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
128{
129 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
130 iewQueue = iq_ptr;
131
132 // Setup wire to get instructions from IEW.
133 fromIEW = iewQueue->getWire(-iewToCommitDelay);
134}
135
136template <class Impl>
137void
291{
292 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
293 iewQueue = iq_ptr;
294
295 // Setup wire to get instructions from IEW.
296 fromIEW = iewQueue->getWire(-iewToCommitDelay);
297}
298
299template <class Impl>
300void
138SimpleCommit<Impl>::setROB(ROB *rob_ptr)
301DefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage)
139{
302{
303 fetchStage = fetch_stage;
304}
305
306template <class Impl>
307void
308DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
309{
310 iewStage = iew_stage;
311}
312
313template<class Impl>
314void
315DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr)
316{
317 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
318 activeThreads = at_ptr;
319}
320
321template <class Impl>
322void
323DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
324{
325 DPRINTF(Commit, "Setting rename map pointers.\n");
326
327 for (int i=0; i < numThreads; i++) {
328 renameMap[i] = &rm_ptr[i];
329 }
330}
331
332template <class Impl>
333void
334DefaultCommit<Impl>::setROB(ROB *rob_ptr)
335{
140 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
141 rob = rob_ptr;
142}
143
144template <class Impl>
145void
336 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
337 rob = rob_ptr;
338}
339
340template <class Impl>
341void
146SimpleCommit<Impl>::tick()
342DefaultCommit<Impl>::initStage()
147{
343{
148 // If the ROB is currently in its squash sequence, then continue
149 // to squash. In this case, commit does not do anything. Otherwise
150 // run commit.
151 if (_status == ROBSquashing) {
152 if (rob->isDoneSquashing()) {
153 _status = Running;
154 } else {
155 rob->doSquash();
344 rob->setActiveThreads(activeThreads);
345 rob->resetEntries();
156
346
157 // Send back sequence number of tail of ROB, so other stages
158 // can squash younger instructions. Note that really the only
159 // stage that this is important for is the IEW stage; other
160 // stages can just clear all their state as long as selective
161 // replay isn't used.
162 toIEW->commitInfo.doneSeqNum = rob->readTailSeqNum();
163 toIEW->commitInfo.robSquashing = true;
347 // Broadcast the number of free entries.
348 for (int i=0; i < numThreads; i++) {
349 toIEW->commitInfo[i].usedROB = true;
350 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
351 }
352
353 cpu->activityThisCycle();
354}
355
356template <class Impl>
357void
358DefaultCommit<Impl>::switchOut()
359{
360 switchPending = true;
361}
362
363template <class Impl>
364void
365DefaultCommit<Impl>::doSwitchOut()
366{
367 switchedOut = true;
368 switchPending = false;
369 rob->switchOut();
370}
371
372template <class Impl>
373void
374DefaultCommit<Impl>::takeOverFrom()
375{
376 switchedOut = false;
377 _status = Active;
378 _nextStatus = Inactive;
379 for (int i=0; i < numThreads; i++) {
380 commitStatus[i] = Idle;
381 changedROBNumEntries[i] = false;
382 trapSquash[i] = false;
383 xcSquash[i] = false;
384 }
385 squashCounter = 0;
386 rob->takeOverFrom();
387}
388
389template <class Impl>
390void
391DefaultCommit<Impl>::updateStatus()
392{
393 // reset ROB changed variable
394 list<unsigned>::iterator threads = (*activeThreads).begin();
395 while (threads != (*activeThreads).end()) {
396 unsigned tid = *threads++;
397 changedROBNumEntries[tid] = false;
398
399 // Also check if any of the threads has a trap pending
400 if (commitStatus[tid] == TrapPending ||
401 commitStatus[tid] == FetchTrapPending) {
402 _nextStatus = Active;
164 }
403 }
165 } else {
166 commit();
167 }
168
404 }
405
406 if (_nextStatus == Inactive && _status == Active) {
407 DPRINTF(Activity, "Deactivating stage.\n");
408 cpu->deactivateStage(FullCPU::CommitIdx);
409 } else if (_nextStatus == Active && _status == Inactive) {
410 DPRINTF(Activity, "Activating stage.\n");
411 cpu->activateStage(FullCPU::CommitIdx);
412 }
413
414 _status = _nextStatus;
415}
416
417template <class Impl>
418void
419DefaultCommit<Impl>::setNextStatus()
420{
421 int squashes = 0;
422
423 list<unsigned>::iterator threads = (*activeThreads).begin();
424
425 while (threads != (*activeThreads).end()) {
426 unsigned tid = *threads++;
427
428 if (commitStatus[tid] == ROBSquashing) {
429 squashes++;
430 }
431 }
432
433 assert(squashes == squashCounter);
434
435 // If commit is currently squashing, then it will have activity for the
436 // next cycle. Set its next status as active.
437 if (squashCounter) {
438 _nextStatus = Active;
439 }
440}
441
442template <class Impl>
443bool
444DefaultCommit<Impl>::changedROBEntries()
445{
446 list<unsigned>::iterator threads = (*activeThreads).begin();
447
448 while (threads != (*activeThreads).end()) {
449 unsigned tid = *threads++;
450
451 if (changedROBNumEntries[tid]) {
452 return true;
453 }
454 }
455
456 return false;
457}
458
459template <class Impl>
460unsigned
461DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
462{
463 return rob->numFreeEntries(tid);
464}
465
466template <class Impl>
467void
468DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
469{
470 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
471
472 TrapEvent *trap = new TrapEvent(this, tid);
473
474 trap->schedule(curTick + trapLatency);
475
476 thread[tid]->trapPending = true;
477}
478
479template <class Impl>
480void
481DefaultCommit<Impl>::generateXCEvent(unsigned tid)
482{
483 DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid);
484
485 xcSquash[tid] = true;
486}
487
488template <class Impl>
489void
490DefaultCommit<Impl>::squashAll(unsigned tid)
491{
492 // If we want to include the squashing instruction in the squash,
493 // then use one older sequence number.
494 // Hopefully this doesn't mess things up. Basically I want to squash
495 // all instructions of this thread.
496 InstSeqNum squashed_inst = rob->isEmpty() ?
497 0 : rob->readHeadInst(tid)->seqNum - 1;;
498
499 // All younger instructions will be squashed. Set the sequence
500 // number as the youngest instruction in the ROB (0 in this case.
501 // Hopefully nothing breaks.)
502 youngestSeqNum[tid] = 0;
503
504 rob->squash(squashed_inst, tid);
505 changedROBNumEntries[tid] = true;
506
507 // Send back the sequence number of the squashed instruction.
508 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
509
510 // Send back the squash signal to tell stages that they should
511 // squash.
512 toIEW->commitInfo[tid].squash = true;
513
514 // Send back the rob squashing signal so other stages know that
515 // the ROB is in the process of squashing.
516 toIEW->commitInfo[tid].robSquashing = true;
517
518 toIEW->commitInfo[tid].branchMispredict = false;
519
520 toIEW->commitInfo[tid].nextPC = PC[tid];
521}
522
523template <class Impl>
524void
525DefaultCommit<Impl>::squashFromTrap(unsigned tid)
526{
527 squashAll(tid);
528
529 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
530
531 thread[tid]->trapPending = false;
532 thread[tid]->inSyscall = false;
533
534 trapSquash[tid] = false;
535
536 commitStatus[tid] = ROBSquashing;
537 cpu->activityThisCycle();
538
539 ++squashCounter;
540}
541
542template <class Impl>
543void
544DefaultCommit<Impl>::squashFromXC(unsigned tid)
545{
546 squashAll(tid);
547
548 DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]);
549
550 thread[tid]->inSyscall = false;
551 assert(!thread[tid]->trapPending);
552
553 commitStatus[tid] = ROBSquashing;
554 cpu->activityThisCycle();
555
556 xcSquash[tid] = false;
557
558 ++squashCounter;
559}
560
561template <class Impl>
562void
563DefaultCommit<Impl>::tick()
564{
565 wroteToTimeBuffer = false;
566 _nextStatus = Inactive;
567
568 if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
569 cpu->signalSwitched();
570 return;
571 }
572
573 list<unsigned>::iterator threads = (*activeThreads).begin();
574
575 // Check if any of the threads are done squashing. Change the
576 // status if they are done.
577 while (threads != (*activeThreads).end()) {
578 unsigned tid = *threads++;
579
580 if (commitStatus[tid] == ROBSquashing) {
581
582 if (rob->isDoneSquashing(tid)) {
583 commitStatus[tid] = Running;
584 --squashCounter;
585 } else {
586 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
587 "insts this cycle.\n", tid);
588 }
589 }
590 }
591
592 commit();
593
169 markCompletedInsts();
170
594 markCompletedInsts();
595
171 // Writeback number of free ROB entries here.
172 DPRINTF(Commit, "Commit: ROB has %d free entries.\n",
173 rob->numFreeEntries());
174 toIEW->commitInfo.freeROBEntries = rob->numFreeEntries();
596 threads = (*activeThreads).begin();
597
598 while (threads != (*activeThreads).end()) {
599 unsigned tid = *threads++;
600
601 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
602 // The ROB has more instructions it can commit. Its next status
603 // will be active.
604 _nextStatus = Active;
605
606 DynInstPtr inst = rob->readHeadInst(tid);
607
608 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
609 " ROB and ready to commit\n",
610 tid, inst->seqNum, inst->readPC());
611
612 } else if (!rob->isEmpty(tid)) {
613 DynInstPtr inst = rob->readHeadInst(tid);
614
615 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
616 "%#x is head of ROB and not ready\n",
617 tid, inst->seqNum, inst->readPC());
618 }
619
620 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
621 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
622 }
623
624
625 if (wroteToTimeBuffer) {
626 DPRINTF(Activity, "Activity This Cycle.\n");
627 cpu->activityThisCycle();
628 }
629
630 updateStatus();
175}
176
177template <class Impl>
178void
631}
632
633template <class Impl>
634void
179SimpleCommit<Impl>::commit()
635DefaultCommit<Impl>::commit()
180{
636{
637
181 //////////////////////////////////////
182 // Check for interrupts
183 //////////////////////////////////////
184
638 //////////////////////////////////////
639 // Check for interrupts
640 //////////////////////////////////////
641
185 // Process interrupts if interrupts are enabled and not in PAL mode.
186 // Take the PC from commit and write it to the IPR, then squash. The
187 // interrupt completing will take care of restoring the PC from that value
188 // in the IPR. Look at IPR[EXC_ADDR];
189 // hwrei() is what resets the PC to the place where instruction execution
190 // beings again.
191#if FULL_SYSTEM
642#if FULL_SYSTEM
192 if (//checkInterrupts &&
643 // Process interrupts if interrupts are enabled, not in PAL mode,
644 // and no other traps or external squashes are currently pending.
645 // @todo: Allow other threads to handle interrupts.
646 if (cpu->checkInterrupts &&
193 cpu->check_interrupts() &&
647 cpu->check_interrupts() &&
194 !cpu->inPalMode(readCommitPC())) {
195 // Will need to squash all instructions currently in flight and have
196 // the interrupt handler restart at the last non-committed inst.
197 // Most of that can be handled through the trap() function. The
198 // processInterrupts() function really just checks for interrupts
199 // and then calls trap() if there is an interrupt present.
648 !cpu->inPalMode(readPC()) &&
649 !trapSquash[0] &&
650 !xcSquash[0]) {
651 // Tell fetch that there is an interrupt pending. This will
652 // make fetch wait until it sees a non PAL-mode PC, at which
653 // point it stops fetching instructions.
654 toIEW->commitInfo[0].interruptPending = true;
200
655
201 // CPU will handle implementation of the interrupt.
202 cpu->processInterrupts();
656 // Wait until the ROB is empty and all stores have drained in
657 // order to enter the interrupt.
658 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
659 // Not sure which thread should be the one to interrupt. For now
660 // always do thread 0.
661 assert(!thread[0]->inSyscall);
662 thread[0]->inSyscall = true;
663
664 // CPU will handle implementation of the interrupt.
665 cpu->processInterrupts();
666
667 // Now squash or record that I need to squash this cycle.
668 commitStatus[0] = TrapPending;
669
670 // Exit state update mode to avoid accidental updating.
671 thread[0]->inSyscall = false;
672
673 // Generate trap squash event.
674 generateTrapEvent(0);
675
676 toIEW->commitInfo[0].clearInterrupt = true;
677
678 DPRINTF(Commit, "Interrupt detected.\n");
679 } else {
680 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
681 }
203 }
204#endif // FULL_SYSTEM
205
206 ////////////////////////////////////
682 }
683#endif // FULL_SYSTEM
684
685 ////////////////////////////////////
207 // Check for squash signal, handle that first
686 // Check for any possible squashes, handle them first
208 ////////////////////////////////////
209
687 ////////////////////////////////////
688
210 // Want to mainly check if the IEW stage is telling the ROB to squash.
211 // Should I also check if the commit stage is telling the ROB to squah?
212 // This might be necessary to keep the same timing between the IQ and
213 // the ROB...
214 if (fromIEW->squash) {
215 DPRINTF(Commit, "Commit: Squashing instructions in the ROB.\n");
689 list<unsigned>::iterator threads = (*activeThreads).begin();
216
690
217 _status = ROBSquashing;
691 while (threads != (*activeThreads).end()) {
692 unsigned tid = *threads++;
218
693
219 InstSeqNum squashed_inst = fromIEW->squashedSeqNum;
694 if (fromFetch->fetchFault && commitStatus[0] != TrapPending) {
695 // Record the fault. Wait until it's empty in the ROB.
696 // Then handle the trap. Ignore it if there's already a
697 // trap pending as fetch will be redirected.
698 fetchFault = fromFetch->fetchFault;
699 fetchFaultTick = curTick + fetchTrapLatency;
700 commitStatus[0] = FetchTrapPending;
701 DPRINTF(Commit, "Fault from fetch recorded. Will trap if the "
702 "ROB empties without squashing the fault.\n");
703 fetchTrapWait = 0;
704 }
220
705
221 rob->squash(squashed_inst);
706 // Fetch may tell commit to clear the trap if it's been squashed.
707 if (fromFetch->clearFetchFault) {
708 DPRINTF(Commit, "Received clear fetch fault signal\n");
709 fetchTrapWait = 0;
710 if (commitStatus[0] == FetchTrapPending) {
711 DPRINTF(Commit, "Clearing fault from fetch\n");
712 commitStatus[0] = Running;
713 }
714 }
222
715
223 // Send back the sequence number of the squashed instruction.
224 toIEW->commitInfo.doneSeqNum = squashed_inst;
716 // Not sure which one takes priority. I think if we have
717 // both, that's a bad sign.
718 if (trapSquash[tid] == true) {
719 assert(!xcSquash[tid]);
720 squashFromTrap(tid);
721 } else if (xcSquash[tid] == true) {
722 squashFromXC(tid);
723 }
225
724
226 // Send back the squash signal to tell stages that they should squash.
227 toIEW->commitInfo.squash = true;
725 // Squashed sequence number must be older than youngest valid
726 // instruction in the ROB. This prevents squashes from younger
727 // instructions overriding squashes from older instructions.
728 if (fromIEW->squash[tid] &&
729 commitStatus[tid] != TrapPending &&
730 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
228
731
229 // Send back the rob squashing signal so other stages know that the
230 // ROB is in the process of squashing.
231 toIEW->commitInfo.robSquashing = true;
732 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
733 tid,
734 fromIEW->mispredPC[tid],
735 fromIEW->squashedSeqNum[tid]);
232
736
233 toIEW->commitInfo.branchMispredict = fromIEW->branchMispredict;
737 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
738 tid,
739 fromIEW->nextPC[tid]);
234
740
235 toIEW->commitInfo.branchTaken = fromIEW->branchTaken;
741 commitStatus[tid] = ROBSquashing;
236
742
237 toIEW->commitInfo.nextPC = fromIEW->nextPC;
743 ++squashCounter;
238
744
239 toIEW->commitInfo.mispredPC = fromIEW->mispredPC;
745 // If we want to include the squashing instruction in the squash,
746 // then use one older sequence number.
747 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
240
748
241 if (toIEW->commitInfo.branchMispredict) {
242 ++branchMispredicts;
749 if (fromIEW->includeSquashInst[tid] == true)
750 squashed_inst--;
751
752 // All younger instructions will be squashed. Set the sequence
753 // number as the youngest instruction in the ROB.
754 youngestSeqNum[tid] = squashed_inst;
755
756 rob->squash(squashed_inst, tid);
757 changedROBNumEntries[tid] = true;
758
759 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
760
761 toIEW->commitInfo[tid].squash = true;
762
763 // Send back the rob squashing signal so other stages know that
764 // the ROB is in the process of squashing.
765 toIEW->commitInfo[tid].robSquashing = true;
766
767 toIEW->commitInfo[tid].branchMispredict =
768 fromIEW->branchMispredict[tid];
769
770 toIEW->commitInfo[tid].branchTaken =
771 fromIEW->branchTaken[tid];
772
773 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
774
775 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
776
777 if (toIEW->commitInfo[tid].branchMispredict) {
778 ++branchMispredicts;
779 }
243 }
780 }
781
244 }
245
782 }
783
246 if (_status != ROBSquashing) {
784 setNextStatus();
785
786 if (squashCounter != numThreads) {
247 // If we're not currently squashing, then get instructions.
248 getInsts();
249
250 // Try to commit any instructions.
251 commitInsts();
252 }
253
787 // If we're not currently squashing, then get instructions.
788 getInsts();
789
790 // Try to commit any instructions.
791 commitInsts();
792 }
793
254 // If the ROB is empty, we can set this stage to idle. Use this
255 // in the future when the Idle status will actually be utilized.
256#if 0
257 if (rob->isEmpty()) {
258 DPRINTF(Commit, "Commit: ROB is empty. Status changed to idle.\n");
259 _status = Idle;
260 // Schedule an event so that commit will actually wake up
261 // once something gets put in the ROB.
794 //Check for any activity
795 threads = (*activeThreads).begin();
796
797 while (threads != (*activeThreads).end()) {
798 unsigned tid = *threads++;
799
800 if (changedROBNumEntries[tid]) {
801 toIEW->commitInfo[tid].usedROB = true;
802 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
803
804 if (rob->isEmpty(tid)) {
805 toIEW->commitInfo[tid].emptyROB = true;
806 }
807
808 wroteToTimeBuffer = true;
809 changedROBNumEntries[tid] = false;
810 }
262 }
811 }
263#endif
264}
265
812}
813
266// Loop that goes through as many instructions in the ROB as possible and
267// tries to commit them. The actual work for committing is done by the
268// commitHead() function.
269template <class Impl>
270void
814template <class Impl>
815void
271SimpleCommit<Impl>::commitInsts()
816DefaultCommit<Impl>::commitInsts()
272{
273 ////////////////////////////////////
274 // Handle commit
817{
818 ////////////////////////////////////
819 // Handle commit
275 // Note that commit will be handled prior to the ROB so that the ROB
276 // only tries to commit instructions it has in this current cycle, and
277 // not instructions it is writing in during this cycle.
278 // Can't commit and squash things at the same time...
820 // Note that commit will be handled prior to putting new
821 // instructions in the ROB so that the ROB only tries to commit
822 // instructions it has in this current cycle, and not instructions
823 // it is writing in during this cycle. Can't commit and squash
824 // things at the same time...
279 ////////////////////////////////////
280
825 ////////////////////////////////////
826
281 if (rob->isEmpty())
282 return;
827 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
283
828
284 DynInstPtr head_inst = rob->readHeadInst();
285
286 unsigned num_committed = 0;
287
829 unsigned num_committed = 0;
830
831 DynInstPtr head_inst;
832
288 // Commit as many instructions as possible until the commit bandwidth
289 // limit is reached, or it becomes impossible to commit any more.
833 // Commit as many instructions as possible until the commit bandwidth
834 // limit is reached, or it becomes impossible to commit any more.
290 while (!rob->isEmpty() &&
291 head_inst->readyToCommit() &&
292 num_committed < commitWidth)
293 {
294 DPRINTF(Commit, "Commit: Trying to commit head instruction.\n");
835 while (num_committed < commitWidth) {
836 int commit_thread = getCommittingThread();
295
837
296 // If the head instruction is squashed, it is ready to retire at any
297 // time. However, we need to avoid updating any other state
298 // incorrectly if it's already been squashed.
838 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
839 break;
840
841 head_inst = rob->readHeadInst(commit_thread);
842
843 int tid = head_inst->threadNumber;
844
845 assert(tid == commit_thread);
846
847 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
848 head_inst->seqNum, tid);
849
850 // If the head instruction is squashed, it is ready to retire
851 // (be removed from the ROB) at any time.
299 if (head_inst->isSquashed()) {
300
852 if (head_inst->isSquashed()) {
853
301 DPRINTF(Commit, "Commit: Retiring squashed instruction from "
854 DPRINTF(Commit, "Retiring squashed instruction from "
302 "ROB.\n");
303
855 "ROB.\n");
856
304 // Tell ROB to retire head instruction. This retires the head
305 // inst in the ROB without affecting any other stages.
306 rob->retireHead();
857 rob->retireHead(commit_thread);
307
308 ++commitSquashedInsts;
309
858
859 ++commitSquashedInsts;
860
861 // Record that the number of ROB entries has changed.
862 changedROBNumEntries[tid] = true;
310 } else {
863 } else {
864 PC[tid] = head_inst->readPC();
865 nextPC[tid] = head_inst->readNextPC();
866
311 // Increment the total number of non-speculative instructions
312 // executed.
313 // Hack for now: it really shouldn't happen until after the
314 // commit is deemed to be successful, but this count is needed
315 // for syscalls.
867 // Increment the total number of non-speculative instructions
868 // executed.
869 // Hack for now: it really shouldn't happen until after the
870 // commit is deemed to be successful, but this count is needed
871 // for syscalls.
316 cpu->funcExeInst++;
872 thread[tid]->funcExeInst++;
317
318 // Try to commit the head instruction.
319 bool commit_success = commitHead(head_inst, num_committed);
320
873
874 // Try to commit the head instruction.
875 bool commit_success = commitHead(head_inst, num_committed);
876
321 // Update what instruction we are looking at if the commit worked.
322 if (commit_success) {
323 ++num_committed;
324
877 if (commit_success) {
878 ++num_committed;
879
325 // Send back which instruction has been committed.
326 // @todo: Update this later when a wider pipeline is used.
327 // Hmm, can't really give a pointer here...perhaps the
328 // sequence number instead (copy).
329 toIEW->commitInfo.doneSeqNum = head_inst->seqNum;
880 changedROBNumEntries[tid] = true;
330
881
882 // Set the doneSeqNum to the youngest committed instruction.
883 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
884
331 ++commitCommittedInsts;
332
885 ++commitCommittedInsts;
886
333 if (!head_inst->isNop()) {
334 cpu->instDone();
887 // To match the old model, don't count nops and instruction
888 // prefetches towards the total commit count.
889 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
890 cpu->instDone(tid);
335 }
891 }
892
893 PC[tid] = nextPC[tid];
894 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
895#if FULL_SYSTEM
896 int count = 0;
897 Addr oldpc;
898 do {
899 // Debug statement. Checks to make sure we're not
900 // currently updating state while handling PC events.
901 if (count == 0)
902 assert(!thread[tid]->inSyscall &&
903 !thread[tid]->trapPending);
904 oldpc = PC[tid];
905 cpu->system->pcEventQueue.service(
906 thread[tid]->getXCProxy());
907 count++;
908 } while (oldpc != PC[tid]);
909 if (count > 1) {
910 DPRINTF(Commit, "PC skip function event, stopping commit\n");
911 break;
912 }
913#endif
336 } else {
914 } else {
915 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
916 "[tid:%i] [sn:%i].\n",
917 head_inst->readPC(), tid ,head_inst->seqNum);
337 break;
338 }
339 }
918 break;
919 }
920 }
340
341 // Update the pointer to read the next instruction in the ROB.
342 head_inst = rob->readHeadInst();
343 }
344
345 DPRINTF(CommitRate, "%i\n", num_committed);
921 }
922
923 DPRINTF(CommitRate, "%i\n", num_committed);
346 n_committed_dist.sample(num_committed);
924 numCommittedDist.sample(num_committed);
925
926 if (num_committed == commitWidth) {
927 commitEligible[0]++;
928 }
347}
348
349template <class Impl>
350bool
929}
930
931template <class Impl>
932bool
351SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
933DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
352{
934{
353 // Make sure instruction is valid
354 assert(head_inst);
355
935 assert(head_inst);
936
356 // If the instruction is not executed yet, then it is a non-speculative
357 // or store inst. Signal backwards that it should be executed.
937 int tid = head_inst->threadNumber;
938
939 // If the instruction is not executed yet, then it will need extra
940 // handling. Signal backwards that it should be executed.
358 if (!head_inst->isExecuted()) {
359 // Keep this number correct. We have not yet actually executed
360 // and committed this instruction.
941 if (!head_inst->isExecuted()) {
942 // Keep this number correct. We have not yet actually executed
943 // and committed this instruction.
361 cpu->funcExeInst--;
944 thread[tid]->funcExeInst--;
362
945
363 if (head_inst->isNonSpeculative()) {
364 DPRINTF(Commit, "Commit: Encountered a store or non-speculative "
365 "instruction at the head of the ROB, PC %#x.\n",
366 head_inst->readPC());
946 head_inst->reachedCommit = true;
367
947
368 toIEW->commitInfo.nonSpecSeqNum = head_inst->seqNum;
948 if (head_inst->isNonSpeculative() ||
949 head_inst->isMemBarrier() ||
950 head_inst->isWriteBarrier()) {
369
951
952 DPRINTF(Commit, "Encountered a barrier or non-speculative "
953 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
954 head_inst->seqNum, head_inst->readPC());
955
956#if !FULL_SYSTEM
957 // Hack to make sure syscalls/memory barriers/quiesces
958 // aren't executed until all stores write back their data.
959 // This direct communication shouldn't be used for
960 // anything other than this.
961 if (inst_num > 0 || iewStage->hasStoresToWB())
962#else
963 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
964 head_inst->isQuiesce()) &&
965 iewStage->hasStoresToWB())
966#endif
967 {
968 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
969 return false;
970 }
971
972 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
973
370 // Change the instruction so it won't try to commit again until
371 // it is executed.
372 head_inst->clearCanCommit();
373
374 ++commitNonSpecStalls;
375
376 return false;
974 // Change the instruction so it won't try to commit again until
975 // it is executed.
976 head_inst->clearCanCommit();
977
978 ++commitNonSpecStalls;
979
980 return false;
981 } else if (head_inst->isLoad()) {
982 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
983 head_inst->seqNum, head_inst->readPC());
984
985 // Send back the non-speculative instruction's sequence
986 // number. Tell the lsq to re-execute the load.
987 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
988 toIEW->commitInfo[tid].uncached = true;
989 toIEW->commitInfo[tid].uncachedLoad = head_inst;
990
991 head_inst->clearCanCommit();
992
993 return false;
377 } else {
994 } else {
378 panic("Commit: Trying to commit un-executed instruction "
995 panic("Trying to commit un-executed instruction "
379 "of unknown type!\n");
380 }
381 }
382
996 "of unknown type!\n");
997 }
998 }
999
383 // Now check if it's one of the special trap or barrier or
384 // serializing instructions.
385 if (head_inst->isThreadSync() ||
386 head_inst->isSerializing() ||
387 head_inst->isMemBarrier() ||
388 head_inst->isWriteBarrier() )
389 {
390 // Not handled for now. Mem barriers and write barriers are safe
391 // to simply let commit as memory accesses only happen once they
392 // reach the head of commit. Not sure about the other two.
393 panic("Serializing or barrier instructions"
394 " are not handled yet.\n");
1000 if (head_inst->isThreadSync()) {
1001 // Not handled for now.
1002 panic("Thread sync instructions are not handled yet.\n");
395 }
396
1003 }
1004
1005 // Stores mark themselves as completed.
1006 if (!head_inst->isStore()) {
1007 head_inst->setCompleted();
1008 }
1009
1010 // Use checker prior to updating anything due to traps or PC
1011 // based events.
1012 if (cpu->checker) {
1013 cpu->checker->tick(head_inst);
1014 }
1015
397 // Check if the instruction caused a fault. If so, trap.
398 Fault inst_fault = head_inst->getFault();
399
400 if (inst_fault != NoFault) {
1016 // Check if the instruction caused a fault. If so, trap.
1017 Fault inst_fault = head_inst->getFault();
1018
1019 if (inst_fault != NoFault) {
401 if (!head_inst->isNop()) {
1020 head_inst->setCompleted();
402#if FULL_SYSTEM
1021#if FULL_SYSTEM
403 cpu->trap(inst_fault);
404#else // !FULL_SYSTEM
405 panic("fault (%d) detected @ PC %08p", inst_fault,
406 head_inst->PC);
407#endif // FULL_SYSTEM
1022 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1023 head_inst->seqNum, head_inst->readPC());
1024
1025 if (iewStage->hasStoresToWB() || inst_num > 0) {
1026 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1027 return false;
408 }
1028 }
409 }
410
1029
411 // Check if we're really ready to commit. If not then return false.
412 // I'm pretty sure all instructions should be able to commit if they've
413 // reached this far. For now leave this in as a check.
414 if (!rob->isHeadReady()) {
415 panic("Commit: Unable to commit head instruction!\n");
416 return false;
417 }
1030 if (cpu->checker && head_inst->isStore()) {
1031 cpu->checker->tick(head_inst);
1032 }
418
1033
419 // If it's a branch, then send back branch prediction update info
420 // to the fetch stage.
421 // This should be handled in the iew stage if a mispredict happens...
1034 assert(!thread[tid]->inSyscall);
422
1035
423 if (head_inst->isControl()) {
1036 // Mark that we're in state update mode so that the trap's
1037 // execution doesn't generate extra squashes.
1038 thread[tid]->inSyscall = true;
424
1039
425#if 0
426 toIEW->nextPC = head_inst->readPC();
427 //Maybe switch over to BTB incorrect.
428 toIEW->btbMissed = head_inst->btbMiss();
429 toIEW->target = head_inst->nextPC;
430 //Maybe also include global history information.
431 //This simple version will have no branch prediction however.
432#endif
1040 // DTB will sometimes need the machine instruction for when
1041 // faults happen. So we will set it here, prior to the DTB
1042 // possibly needing it for its fault.
1043 thread[tid]->setInst(
1044 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
433
1045
434 ++commitCommittedBranches;
1046 // Execute the trap. Although it's slightly unrealistic in
1047 // terms of timing (as it doesn't wait for the full timing of
1048 // the trap event to complete before updating state), it's
1049 // needed to update the state as soon as possible. This
1050 // prevents external agents from changing any specific state
1051 // that the trap need.
1052 cpu->trap(inst_fault, tid);
1053
1054 // Exit state update mode to avoid accidental updating.
1055 thread[tid]->inSyscall = false;
1056
1057 commitStatus[tid] = TrapPending;
1058
1059 // Generate trap squash event.
1060 generateTrapEvent(tid);
1061
1062 return false;
1063#else // !FULL_SYSTEM
1064 panic("fault (%d) detected @ PC %08p", inst_fault,
1065 head_inst->PC);
1066#endif // FULL_SYSTEM
435 }
436
1067 }
1068
437 // Now that the instruction is going to be committed, finalize its
438 // trace data.
1069 updateComInstStats(head_inst);
1070
439 if (head_inst->traceData) {
1071 if (head_inst->traceData) {
1072 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1073 head_inst->traceData->setCPSeq(thread[tid]->numInst);
440 head_inst->traceData->finalize();
1074 head_inst->traceData->finalize();
1075 head_inst->traceData = NULL;
441 }
442
1076 }
1077
443 //Finally clear the head ROB entry.
444 rob->retireHead();
1078 // Update the commit rename map
1079 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1080 renameMap[tid]->setEntry(head_inst->destRegIdx(i),
1081 head_inst->renamedDestRegIdx(i));
1082 }
445
1083
1084 // Finally clear the head ROB entry.
1085 rob->retireHead(tid);
1086
446 // Return true to indicate that we have committed an instruction.
447 return true;
448}
449
450template <class Impl>
451void
1087 // Return true to indicate that we have committed an instruction.
1088 return true;
1089}
1090
1091template <class Impl>
1092void
452SimpleCommit<Impl>::getInsts()
1093DefaultCommit<Impl>::getInsts()
453{
1094{
454 //////////////////////////////////////
455 // Handle ROB functions
456 //////////////////////////////////////
457
458 // Read any issued instructions and place them into the ROB. Do this
459 // prior to squashing to avoid having instructions in the ROB that
460 // don't get squashed properly.
1095 // Read any renamed instructions and place them into the ROB.
461 int insts_to_process = min((int)renameWidth, fromRename->size);
462
1096 int insts_to_process = min((int)renameWidth, fromRename->size);
1097
463 for (int inst_num = 0;
464 inst_num < insts_to_process;
465 ++inst_num)
1098 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num)
466 {
1099 {
467 if (!fromRename->insts[inst_num]->isSquashed()) {
468 DPRINTF(Commit, "Commit: Inserting PC %#x into ROB.\n",
469 fromRename->insts[inst_num]->readPC());
470 rob->insertInst(fromRename->insts[inst_num]);
1100 DynInstPtr inst = fromRename->insts[inst_num];
1101 int tid = inst->threadNumber;
1102
1103 if (!inst->isSquashed() &&
1104 commitStatus[tid] != ROBSquashing) {
1105 changedROBNumEntries[tid] = true;
1106
1107 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1108 inst->readPC(), inst->seqNum, tid);
1109
1110 rob->insertInst(inst);
1111
1112 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1113
1114 youngestSeqNum[tid] = inst->seqNum;
471 } else {
1115 } else {
472 DPRINTF(Commit, "Commit: Instruction %i PC %#x was "
1116 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
473 "squashed, skipping.\n",
1117 "squashed, skipping.\n",
474 fromRename->insts[inst_num]->seqNum,
475 fromRename->insts[inst_num]->readPC());
1118 inst->readPC(), inst->seqNum, tid);
476 }
477 }
478}
479
480template <class Impl>
481void
1119 }
1120 }
1121}
1122
1123template <class Impl>
1124void
482SimpleCommit<Impl>::markCompletedInsts()
1125DefaultCommit<Impl>::markCompletedInsts()
483{
484 // Grab completed insts out of the IEW instruction queue, and mark
485 // instructions completed within the ROB.
486 for (int inst_num = 0;
487 inst_num < fromIEW->size && fromIEW->insts[inst_num];
488 ++inst_num)
489 {
1126{
1127 // Grab completed insts out of the IEW instruction queue, and mark
1128 // instructions completed within the ROB.
1129 for (int inst_num = 0;
1130 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1131 ++inst_num)
1132 {
490 DPRINTF(Commit, "Commit: Marking PC %#x, SN %i ready within ROB.\n",
491 fromIEW->insts[inst_num]->readPC(),
492 fromIEW->insts[inst_num]->seqNum);
1133 if (!fromIEW->insts[inst_num]->isSquashed()) {
1134 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1135 "within ROB.\n",
1136 fromIEW->insts[inst_num]->threadNumber,
1137 fromIEW->insts[inst_num]->readPC(),
1138 fromIEW->insts[inst_num]->seqNum);
493
1139
494 // Mark the instruction as ready to commit.
495 fromIEW->insts[inst_num]->setCanCommit();
1140 // Mark the instruction as ready to commit.
1141 fromIEW->insts[inst_num]->setCanCommit();
1142 }
496 }
497}
498
499template <class Impl>
1143 }
1144}
1145
1146template <class Impl>
500uint64_t
501SimpleCommit<Impl>::readCommitPC()
1147bool
1148DefaultCommit<Impl>::robDoneSquashing()
502{
1149{
503 return rob->readHeadPC();
1150 list<unsigned>::iterator threads = (*activeThreads).begin();
1151
1152 while (threads != (*activeThreads).end()) {
1153 unsigned tid = *threads++;
1154
1155 if (!rob->isDoneSquashing(tid))
1156 return false;
1157 }
1158
1159 return true;
504}
1160}
1161
1162template <class Impl>
1163void
1164DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1165{
1166 unsigned thread = inst->threadNumber;
1167
1168 //
1169 // Pick off the software prefetches
1170 //
1171#ifdef TARGET_ALPHA
1172 if (inst->isDataPrefetch()) {
1173 statComSwp[thread]++;
1174 } else {
1175 statComInst[thread]++;
1176 }
1177#else
1178 statComInst[thread]++;
1179#endif
1180
1181 //
1182 // Control Instructions
1183 //
1184 if (inst->isControl())
1185 statComBranches[thread]++;
1186
1187 //
1188 // Memory references
1189 //
1190 if (inst->isMemRef()) {
1191 statComRefs[thread]++;
1192
1193 if (inst->isLoad()) {
1194 statComLoads[thread]++;
1195 }
1196 }
1197
1198 if (inst->isMemBarrier()) {
1199 statComMembars[thread]++;
1200 }
1201}
1202
1203////////////////////////////////////////
1204// //
1205// SMT COMMIT POLICY MAINTAINED HERE //
1206// //
1207////////////////////////////////////////
1208template <class Impl>
1209int
1210DefaultCommit<Impl>::getCommittingThread()
1211{
1212 if (numThreads > 1) {
1213 switch (commitPolicy) {
1214
1215 case Aggressive:
1216 //If Policy is Aggressive, commit will call
1217 //this function multiple times per
1218 //cycle
1219 return oldestReady();
1220
1221 case RoundRobin:
1222 return roundRobin();
1223
1224 case OldestReady:
1225 return oldestReady();
1226
1227 default:
1228 return -1;
1229 }
1230 } else {
1231 int tid = (*activeThreads).front();
1232
1233 if (commitStatus[tid] == Running ||
1234 commitStatus[tid] == Idle ||
1235 commitStatus[tid] == FetchTrapPending) {
1236 return tid;
1237 } else {
1238 return -1;
1239 }
1240 }
1241}
1242
1243template<class Impl>
1244int
1245DefaultCommit<Impl>::roundRobin()
1246{
1247 list<unsigned>::iterator pri_iter = priority_list.begin();
1248 list<unsigned>::iterator end = priority_list.end();
1249
1250 while (pri_iter != end) {
1251 unsigned tid = *pri_iter;
1252
1253 if (commitStatus[tid] == Running ||
1254 commitStatus[tid] == Idle) {
1255
1256 if (rob->isHeadReady(tid)) {
1257 priority_list.erase(pri_iter);
1258 priority_list.push_back(tid);
1259
1260 return tid;
1261 }
1262 }
1263
1264 pri_iter++;
1265 }
1266
1267 return -1;
1268}
1269
1270template<class Impl>
1271int
1272DefaultCommit<Impl>::oldestReady()
1273{
1274 unsigned oldest = 0;
1275 bool first = true;
1276
1277 list<unsigned>::iterator threads = (*activeThreads).begin();
1278
1279 while (threads != (*activeThreads).end()) {
1280 unsigned tid = *threads++;
1281
1282 if (!rob->isEmpty(tid) &&
1283 (commitStatus[tid] == Running ||
1284 commitStatus[tid] == Idle ||
1285 commitStatus[tid] == FetchTrapPending)) {
1286
1287 if (rob->isHeadReady(tid)) {
1288
1289 DynInstPtr head_inst = rob->readHeadInst(tid);
1290
1291 if (first) {
1292 oldest = tid;
1293 first = false;
1294 } else if (head_inst->seqNum < oldest) {
1295 oldest = tid;
1296 }
1297 }
1298 }
1299 }
1300
1301 if (!first) {
1302 return oldest;
1303 } else {
1304 return -1;
1305 }
1306}