commit_impl.hh (2654:9559cfa91b9d) commit_impl.hh (2665:a124942bacb8)
1/*
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
27 */
28
29 */
30
29#include <algorithm>
30#include <string>
31
32#include "base/loader/symtab.hh"
33#include "base/timebuf.hh"
31#include "base/timebuf.hh"
34#include "cpu/checker/cpu.hh"
35#include "cpu/exetrace.hh"
36#include "cpu/o3/commit.hh"
32#include "cpu/o3/commit.hh"
37#include "cpu/o3/thread_state.hh"
33#include "cpu/exetrace.hh"
38
34
39using namespace std;
40
41template <class Impl>
35template <class Impl>
42DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
43 unsigned _tid)
44 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
36SimpleCommit<Impl>::SimpleCommit(Params &params)
37 : dcacheInterface(params.dcacheInterface),
38 iewToCommitDelay(params.iewToCommitDelay),
39 renameToROBDelay(params.renameToROBDelay),
40 renameWidth(params.renameWidth),
41 iewWidth(params.executeWidth),
42 commitWidth(params.commitWidth)
45{
43{
46 this->setFlags(Event::AutoDelete);
44 _status = Idle;
47}
48
49template <class Impl>
50void
45}
46
47template <class Impl>
48void
51DefaultCommit<Impl>::TrapEvent::process()
49SimpleCommit<Impl>::regStats()
52{
50{
53 // This will get reset by commit if it was switched out at the
54 // time of this event processing.
55 commit->trapSquash[tid] = true;
56}
57
58template <class Impl>
59const char *
60DefaultCommit<Impl>::TrapEvent::description()
61{
62 return "Trap event";
63}
64
65template <class Impl>
66DefaultCommit<Impl>::DefaultCommit(Params *params)
67 : dcacheInterface(params->dcacheInterface),
68 squashCounter(0),
69 iewToCommitDelay(params->iewToCommitDelay),
70 commitToIEWDelay(params->commitToIEWDelay),
71 renameToROBDelay(params->renameToROBDelay),
72 fetchToCommitDelay(params->commitToFetchDelay),
73 renameWidth(params->renameWidth),
74 iewWidth(params->executeWidth),
75 commitWidth(params->commitWidth),
76 numThreads(params->numberOfThreads),
77 switchedOut(false),
78 trapLatency(params->trapLatency),
79 fetchTrapLatency(params->fetchTrapLatency)
80{
81 _status = Active;
82 _nextStatus = Inactive;
83 string policy = params->smtCommitPolicy;
84
85 //Convert string to lowercase
86 std::transform(policy.begin(), policy.end(), policy.begin(),
87 (int(*)(int)) tolower);
88
89 //Assign commit policy
90 if (policy == "aggressive"){
91 commitPolicy = Aggressive;
92
93 DPRINTF(Commit,"Commit Policy set to Aggressive.");
94 } else if (policy == "roundrobin"){
95 commitPolicy = RoundRobin;
96
97 //Set-Up Priority List
98 for (int tid=0; tid < numThreads; tid++) {
99 priority_list.push_back(tid);
100 }
101
102 DPRINTF(Commit,"Commit Policy set to Round Robin.");
103 } else if (policy == "oldestready"){
104 commitPolicy = OldestReady;
105
106 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
107 } else {
108 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
109 "RoundRobin,OldestReady}");
110 }
111
112 for (int i=0; i < numThreads; i++) {
113 commitStatus[i] = Idle;
114 changedROBNumEntries[i] = false;
115 trapSquash[i] = false;
116 xcSquash[i] = false;
117 }
118
119 fetchFaultTick = 0;
120 fetchTrapWait = 0;
121}
122
123template <class Impl>
124std::string
125DefaultCommit<Impl>::name() const
126{
127 return cpu->name() + ".commit";
128}
129
130template <class Impl>
131void
132DefaultCommit<Impl>::regStats()
133{
134 using namespace Stats;
135 commitCommittedInsts
136 .name(name() + ".commitCommittedInsts")
137 .desc("The number of committed instructions")
138 .prereq(commitCommittedInsts);
139 commitSquashedInsts
140 .name(name() + ".commitSquashedInsts")
141 .desc("The number of squashed insts skipped by commit")
142 .prereq(commitSquashedInsts);
143 commitSquashEvents
144 .name(name() + ".commitSquashEvents")
145 .desc("The number of times commit is told to squash")
146 .prereq(commitSquashEvents);
147 commitNonSpecStalls
148 .name(name() + ".commitNonSpecStalls")
149 .desc("The number of times commit has been forced to stall to "
150 "communicate backwards")
151 .prereq(commitNonSpecStalls);
51 commitCommittedInsts
52 .name(name() + ".commitCommittedInsts")
53 .desc("The number of committed instructions")
54 .prereq(commitCommittedInsts);
55 commitSquashedInsts
56 .name(name() + ".commitSquashedInsts")
57 .desc("The number of squashed insts skipped by commit")
58 .prereq(commitSquashedInsts);
59 commitSquashEvents
60 .name(name() + ".commitSquashEvents")
61 .desc("The number of times commit is told to squash")
62 .prereq(commitSquashEvents);
63 commitNonSpecStalls
64 .name(name() + ".commitNonSpecStalls")
65 .desc("The number of times commit has been forced to stall to "
66 "communicate backwards")
67 .prereq(commitNonSpecStalls);
68 commitCommittedBranches
69 .name(name() + ".commitCommittedBranches")
70 .desc("The number of committed branches")
71 .prereq(commitCommittedBranches);
72 commitCommittedLoads
73 .name(name() + ".commitCommittedLoads")
74 .desc("The number of committed loads")
75 .prereq(commitCommittedLoads);
76 commitCommittedMemRefs
77 .name(name() + ".commitCommittedMemRefs")
78 .desc("The number of committed memory references")
79 .prereq(commitCommittedMemRefs);
152 branchMispredicts
153 .name(name() + ".branchMispredicts")
154 .desc("The number of times a branch was mispredicted")
155 .prereq(branchMispredicts);
80 branchMispredicts
81 .name(name() + ".branchMispredicts")
82 .desc("The number of times a branch was mispredicted")
83 .prereq(branchMispredicts);
156 numCommittedDist
84 n_committed_dist
157 .init(0,commitWidth,1)
158 .name(name() + ".COM:committed_per_cycle")
159 .desc("Number of insts commited each cycle")
160 .flags(Stats::pdf)
161 ;
85 .init(0,commitWidth,1)
86 .name(name() + ".COM:committed_per_cycle")
87 .desc("Number of insts commited each cycle")
88 .flags(Stats::pdf)
89 ;
162
163 statComInst
164 .init(cpu->number_of_threads)
165 .name(name() + ".COM:count")
166 .desc("Number of instructions committed")
167 .flags(total)
168 ;
169
170 statComSwp
171 .init(cpu->number_of_threads)
172 .name(name() + ".COM:swp_count")
173 .desc("Number of s/w prefetches committed")
174 .flags(total)
175 ;
176
177 statComRefs
178 .init(cpu->number_of_threads)
179 .name(name() + ".COM:refs")
180 .desc("Number of memory references committed")
181 .flags(total)
182 ;
183
184 statComLoads
185 .init(cpu->number_of_threads)
186 .name(name() + ".COM:loads")
187 .desc("Number of loads committed")
188 .flags(total)
189 ;
190
191 statComMembars
192 .init(cpu->number_of_threads)
193 .name(name() + ".COM:membars")
194 .desc("Number of memory barriers committed")
195 .flags(total)
196 ;
197
198 statComBranches
199 .init(cpu->number_of_threads)
200 .name(name() + ".COM:branches")
201 .desc("Number of branches committed")
202 .flags(total)
203 ;
204
205 //
206 // Commit-Eligible instructions...
207 //
208 // -> The number of instructions eligible to commit in those
209 // cycles where we reached our commit BW limit (less the number
210 // actually committed)
211 //
212 // -> The average value is computed over ALL CYCLES... not just
213 // the BW limited cycles
214 //
215 // -> The standard deviation is computed only over cycles where
216 // we reached the BW limit
217 //
218 commitEligible
219 .init(cpu->number_of_threads)
220 .name(name() + ".COM:bw_limited")
221 .desc("number of insts not committed due to BW limits")
222 .flags(total)
223 ;
224
225 commitEligibleSamples
226 .name(name() + ".COM:bw_lim_events")
227 .desc("number cycles where commit BW limit reached")
228 ;
229}
230
231template <class Impl>
232void
90}
91
92template <class Impl>
93void
233DefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr)
94SimpleCommit<Impl>::setCPU(FullCPU *cpu_ptr)
234{
235 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
236 cpu = cpu_ptr;
95{
96 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
97 cpu = cpu_ptr;
237
238 // Commit must broadcast the number of free entries it has at the start of
239 // the simulation, so it starts as active.
240 cpu->activateStage(FullCPU::CommitIdx);
241
242 trapLatency = cpu->cycles(trapLatency);
243 fetchTrapLatency = cpu->cycles(fetchTrapLatency);
244}
245
246template <class Impl>
247void
98}
99
100template <class Impl>
101void
248DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)
102SimpleCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
249{
103{
250 thread = threads;
251}
252
253template <class Impl>
254void
255DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
256{
257 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
258 timeBuffer = tb_ptr;
259
260 // Setup wire to send information back to IEW.
261 toIEW = timeBuffer->getWire(0);
262
263 // Setup wire to read data from IEW (for the ROB).
264 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
265}
266
267template <class Impl>
268void
104 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
105 timeBuffer = tb_ptr;
106
107 // Setup wire to send information back to IEW.
108 toIEW = timeBuffer->getWire(0);
109
110 // Setup wire to read data from IEW (for the ROB).
111 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
112}
113
114template <class Impl>
115void
269DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
116SimpleCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
270{
117{
271 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
272 fetchQueue = fq_ptr;
273
274 // Setup wire to get instructions from rename (for the ROB).
275 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
276}
277
278template <class Impl>
279void
280DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
281{
282 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
283 renameQueue = rq_ptr;
284
285 // Setup wire to get instructions from rename (for the ROB).
286 fromRename = renameQueue->getWire(-renameToROBDelay);
287}
288
289template <class Impl>
290void
118 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
119 renameQueue = rq_ptr;
120
121 // Setup wire to get instructions from rename (for the ROB).
122 fromRename = renameQueue->getWire(-renameToROBDelay);
123}
124
125template <class Impl>
126void
291DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
127SimpleCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
292{
293 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
294 iewQueue = iq_ptr;
295
296 // Setup wire to get instructions from IEW.
297 fromIEW = iewQueue->getWire(-iewToCommitDelay);
298}
299
300template <class Impl>
301void
128{
129 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
130 iewQueue = iq_ptr;
131
132 // Setup wire to get instructions from IEW.
133 fromIEW = iewQueue->getWire(-iewToCommitDelay);
134}
135
136template <class Impl>
137void
302DefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage)
138SimpleCommit<Impl>::setROB(ROB *rob_ptr)
303{
139{
304 fetchStage = fetch_stage;
305}
306
307template <class Impl>
308void
309DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
310{
311 iewStage = iew_stage;
312}
313
314template<class Impl>
315void
316DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr)
317{
318 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
319 activeThreads = at_ptr;
320}
321
322template <class Impl>
323void
324DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
325{
326 DPRINTF(Commit, "Setting rename map pointers.\n");
327
328 for (int i=0; i < numThreads; i++) {
329 renameMap[i] = &rm_ptr[i];
330 }
331}
332
333template <class Impl>
334void
335DefaultCommit<Impl>::setROB(ROB *rob_ptr)
336{
337 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
338 rob = rob_ptr;
339}
340
341template <class Impl>
342void
140 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
141 rob = rob_ptr;
142}
143
144template <class Impl>
145void
343DefaultCommit<Impl>::initStage()
146SimpleCommit<Impl>::tick()
344{
147{
345 rob->setActiveThreads(activeThreads);
346 rob->resetEntries();
148 // If the ROB is currently in its squash sequence, then continue
149 // to squash. In this case, commit does not do anything. Otherwise
150 // run commit.
151 if (_status == ROBSquashing) {
152 if (rob->isDoneSquashing()) {
153 _status = Running;
154 } else {
155 rob->doSquash();
347
156
348 // Broadcast the number of free entries.
349 for (int i=0; i < numThreads; i++) {
350 toIEW->commitInfo[i].usedROB = true;
351 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
352 }
353
354 cpu->activityThisCycle();
355}
356
357template <class Impl>
358void
359DefaultCommit<Impl>::switchOut()
360{
361 switchPending = true;
362}
363
364template <class Impl>
365void
366DefaultCommit<Impl>::doSwitchOut()
367{
368 switchedOut = true;
369 switchPending = false;
370 rob->switchOut();
371}
372
373template <class Impl>
374void
375DefaultCommit<Impl>::takeOverFrom()
376{
377 switchedOut = false;
378 _status = Active;
379 _nextStatus = Inactive;
380 for (int i=0; i < numThreads; i++) {
381 commitStatus[i] = Idle;
382 changedROBNumEntries[i] = false;
383 trapSquash[i] = false;
384 xcSquash[i] = false;
385 }
386 squashCounter = 0;
387 rob->takeOverFrom();
388}
389
390template <class Impl>
391void
392DefaultCommit<Impl>::updateStatus()
393{
394 // reset ROB changed variable
395 list<unsigned>::iterator threads = (*activeThreads).begin();
396 while (threads != (*activeThreads).end()) {
397 unsigned tid = *threads++;
398 changedROBNumEntries[tid] = false;
399
400 // Also check if any of the threads has a trap pending
401 if (commitStatus[tid] == TrapPending ||
402 commitStatus[tid] == FetchTrapPending) {
403 _nextStatus = Active;
157 // Send back sequence number of tail of ROB, so other stages
158 // can squash younger instructions. Note that really the only
159 // stage that this is important for is the IEW stage; other
160 // stages can just clear all their state as long as selective
161 // replay isn't used.
162 toIEW->commitInfo.doneSeqNum = rob->readTailSeqNum();
163 toIEW->commitInfo.robSquashing = true;
404 }
164 }
165 } else {
166 commit();
405 }
406
167 }
168
407 if (_nextStatus == Inactive && _status == Active) {
408 DPRINTF(Activity, "Deactivating stage.\n");
409 cpu->deactivateStage(FullCPU::CommitIdx);
410 } else if (_nextStatus == Active && _status == Inactive) {
411 DPRINTF(Activity, "Activating stage.\n");
412 cpu->activateStage(FullCPU::CommitIdx);
413 }
414
415 _status = _nextStatus;
416}
417
418template <class Impl>
419void
420DefaultCommit<Impl>::setNextStatus()
421{
422 int squashes = 0;
423
424 list<unsigned>::iterator threads = (*activeThreads).begin();
425
426 while (threads != (*activeThreads).end()) {
427 unsigned tid = *threads++;
428
429 if (commitStatus[tid] == ROBSquashing) {
430 squashes++;
431 }
432 }
433
434 assert(squashes == squashCounter);
435
436 // If commit is currently squashing, then it will have activity for the
437 // next cycle. Set its next status as active.
438 if (squashCounter) {
439 _nextStatus = Active;
440 }
441}
442
443template <class Impl>
444bool
445DefaultCommit<Impl>::changedROBEntries()
446{
447 list<unsigned>::iterator threads = (*activeThreads).begin();
448
449 while (threads != (*activeThreads).end()) {
450 unsigned tid = *threads++;
451
452 if (changedROBNumEntries[tid]) {
453 return true;
454 }
455 }
456
457 return false;
458}
459
460template <class Impl>
461unsigned
462DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
463{
464 return rob->numFreeEntries(tid);
465}
466
467template <class Impl>
468void
469DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
470{
471 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
472
473 TrapEvent *trap = new TrapEvent(this, tid);
474
475 trap->schedule(curTick + trapLatency);
476
477 thread[tid]->trapPending = true;
478}
479
480template <class Impl>
481void
482DefaultCommit<Impl>::generateXCEvent(unsigned tid)
483{
484 DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid);
485
486 xcSquash[tid] = true;
487}
488
489template <class Impl>
490void
491DefaultCommit<Impl>::squashAll(unsigned tid)
492{
493 // If we want to include the squashing instruction in the squash,
494 // then use one older sequence number.
495 // Hopefully this doesn't mess things up. Basically I want to squash
496 // all instructions of this thread.
497 InstSeqNum squashed_inst = rob->isEmpty() ?
498 0 : rob->readHeadInst(tid)->seqNum - 1;;
499
500 // All younger instructions will be squashed. Set the sequence
501 // number as the youngest instruction in the ROB (0 in this case.
502 // Hopefully nothing breaks.)
503 youngestSeqNum[tid] = 0;
504
505 rob->squash(squashed_inst, tid);
506 changedROBNumEntries[tid] = true;
507
508 // Send back the sequence number of the squashed instruction.
509 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
510
511 // Send back the squash signal to tell stages that they should
512 // squash.
513 toIEW->commitInfo[tid].squash = true;
514
515 // Send back the rob squashing signal so other stages know that
516 // the ROB is in the process of squashing.
517 toIEW->commitInfo[tid].robSquashing = true;
518
519 toIEW->commitInfo[tid].branchMispredict = false;
520
521 toIEW->commitInfo[tid].nextPC = PC[tid];
522}
523
524template <class Impl>
525void
526DefaultCommit<Impl>::squashFromTrap(unsigned tid)
527{
528 squashAll(tid);
529
530 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
531
532 thread[tid]->trapPending = false;
533 thread[tid]->inSyscall = false;
534
535 trapSquash[tid] = false;
536
537 commitStatus[tid] = ROBSquashing;
538 cpu->activityThisCycle();
539
540 ++squashCounter;
541}
542
543template <class Impl>
544void
545DefaultCommit<Impl>::squashFromXC(unsigned tid)
546{
547 squashAll(tid);
548
549 DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]);
550
551 thread[tid]->inSyscall = false;
552 assert(!thread[tid]->trapPending);
553
554 commitStatus[tid] = ROBSquashing;
555 cpu->activityThisCycle();
556
557 xcSquash[tid] = false;
558
559 ++squashCounter;
560}
561
562template <class Impl>
563void
564DefaultCommit<Impl>::tick()
565{
566 wroteToTimeBuffer = false;
567 _nextStatus = Inactive;
568
569 if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
570 cpu->signalSwitched();
571 return;
572 }
573
574 list<unsigned>::iterator threads = (*activeThreads).begin();
575
576 // Check if any of the threads are done squashing. Change the
577 // status if they are done.
578 while (threads != (*activeThreads).end()) {
579 unsigned tid = *threads++;
580
581 if (commitStatus[tid] == ROBSquashing) {
582
583 if (rob->isDoneSquashing(tid)) {
584 commitStatus[tid] = Running;
585 --squashCounter;
586 } else {
587 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
588 "insts this cycle.\n", tid);
589 }
590 }
591 }
592
593 commit();
594
595 markCompletedInsts();
596
169 markCompletedInsts();
170
597 threads = (*activeThreads).begin();
598
599 while (threads != (*activeThreads).end()) {
600 unsigned tid = *threads++;
601
602 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
603 // The ROB has more instructions it can commit. Its next status
604 // will be active.
605 _nextStatus = Active;
606
607 DynInstPtr inst = rob->readHeadInst(tid);
608
609 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
610 " ROB and ready to commit\n",
611 tid, inst->seqNum, inst->readPC());
612
613 } else if (!rob->isEmpty(tid)) {
614 DynInstPtr inst = rob->readHeadInst(tid);
615
616 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
617 "%#x is head of ROB and not ready\n",
618 tid, inst->seqNum, inst->readPC());
619 }
620
621 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
622 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
623 }
624
625
626 if (wroteToTimeBuffer) {
627 DPRINTF(Activity, "Activity This Cycle.\n");
628 cpu->activityThisCycle();
629 }
630
631 updateStatus();
171 // Writeback number of free ROB entries here.
172 DPRINTF(Commit, "Commit: ROB has %d free entries.\n",
173 rob->numFreeEntries());
174 toIEW->commitInfo.freeROBEntries = rob->numFreeEntries();
632}
633
634template <class Impl>
635void
175}
176
177template <class Impl>
178void
636DefaultCommit<Impl>::commit()
179SimpleCommit<Impl>::commit()
637{
180{
638
639 //////////////////////////////////////
640 // Check for interrupts
641 //////////////////////////////////////
642
181 //////////////////////////////////////
182 // Check for interrupts
183 //////////////////////////////////////
184
185 // Process interrupts if interrupts are enabled and not in PAL mode.
186 // Take the PC from commit and write it to the IPR, then squash. The
187 // interrupt completing will take care of restoring the PC from that value
188 // in the IPR. Look at IPR[EXC_ADDR];
189 // hwrei() is what resets the PC to the place where instruction execution
190 // beings again.
643#if FULL_SYSTEM
191#if FULL_SYSTEM
644 // Process interrupts if interrupts are enabled, not in PAL mode,
645 // and no other traps or external squashes are currently pending.
646 // @todo: Allow other threads to handle interrupts.
647 if (cpu->checkInterrupts &&
192 if (//checkInterrupts &&
648 cpu->check_interrupts() &&
193 cpu->check_interrupts() &&
649 !cpu->inPalMode(readPC()) &&
650 !trapSquash[0] &&
651 !xcSquash[0]) {
652 // Tell fetch that there is an interrupt pending. This will
653 // make fetch wait until it sees a non PAL-mode PC, at which
654 // point it stops fetching instructions.
655 toIEW->commitInfo[0].interruptPending = true;
194 !cpu->inPalMode(readCommitPC())) {
195 // Will need to squash all instructions currently in flight and have
196 // the interrupt handler restart at the last non-committed inst.
197 // Most of that can be handled through the trap() function. The
198 // processInterrupts() function really just checks for interrupts
199 // and then calls trap() if there is an interrupt present.
656
200
657 // Wait until the ROB is empty and all stores have drained in
658 // order to enter the interrupt.
659 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
660 // Not sure which thread should be the one to interrupt. For now
661 // always do thread 0.
662 assert(!thread[0]->inSyscall);
663 thread[0]->inSyscall = true;
664
665 // CPU will handle implementation of the interrupt.
666 cpu->processInterrupts();
667
668 // Now squash or record that I need to squash this cycle.
669 commitStatus[0] = TrapPending;
670
671 // Exit state update mode to avoid accidental updating.
672 thread[0]->inSyscall = false;
673
674 // Generate trap squash event.
675 generateTrapEvent(0);
676
677 toIEW->commitInfo[0].clearInterrupt = true;
678
679 DPRINTF(Commit, "Interrupt detected.\n");
680 } else {
681 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
682 }
201 // CPU will handle implementation of the interrupt.
202 cpu->processInterrupts();
683 }
684#endif // FULL_SYSTEM
685
686 ////////////////////////////////////
203 }
204#endif // FULL_SYSTEM
205
206 ////////////////////////////////////
687 // Check for any possible squashes, handle them first
207 // Check for squash signal, handle that first
688 ////////////////////////////////////
689
208 ////////////////////////////////////
209
690 list<unsigned>::iterator threads = (*activeThreads).begin();
210 // Want to mainly check if the IEW stage is telling the ROB to squash.
211 // Should I also check if the commit stage is telling the ROB to squah?
212 // This might be necessary to keep the same timing between the IQ and
213 // the ROB...
214 if (fromIEW->squash) {
215 DPRINTF(Commit, "Commit: Squashing instructions in the ROB.\n");
691
216
692 while (threads != (*activeThreads).end()) {
693 unsigned tid = *threads++;
217 _status = ROBSquashing;
694
218
695 if (fromFetch->fetchFault && commitStatus[0] != TrapPending) {
696 // Record the fault. Wait until it's empty in the ROB.
697 // Then handle the trap. Ignore it if there's already a
698 // trap pending as fetch will be redirected.
699 fetchFault = fromFetch->fetchFault;
700 fetchFaultTick = curTick + fetchTrapLatency;
701 commitStatus[0] = FetchTrapPending;
702 DPRINTF(Commit, "Fault from fetch recorded. Will trap if the "
703 "ROB empties without squashing the fault.\n");
704 fetchTrapWait = 0;
705 }
219 InstSeqNum squashed_inst = fromIEW->squashedSeqNum;
706
220
707 // Fetch may tell commit to clear the trap if it's been squashed.
708 if (fromFetch->clearFetchFault) {
709 DPRINTF(Commit, "Received clear fetch fault signal\n");
710 fetchTrapWait = 0;
711 if (commitStatus[0] == FetchTrapPending) {
712 DPRINTF(Commit, "Clearing fault from fetch\n");
713 commitStatus[0] = Running;
714 }
715 }
221 rob->squash(squashed_inst);
716
222
717 // Not sure which one takes priority. I think if we have
718 // both, that's a bad sign.
719 if (trapSquash[tid] == true) {
720 assert(!xcSquash[tid]);
721 squashFromTrap(tid);
722 } else if (xcSquash[tid] == true) {
723 squashFromXC(tid);
724 }
223 // Send back the sequence number of the squashed instruction.
224 toIEW->commitInfo.doneSeqNum = squashed_inst;
725
225
726 // Squashed sequence number must be older than youngest valid
727 // instruction in the ROB. This prevents squashes from younger
728 // instructions overriding squashes from older instructions.
729 if (fromIEW->squash[tid] &&
730 commitStatus[tid] != TrapPending &&
731 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
226 // Send back the squash signal to tell stages that they should squash.
227 toIEW->commitInfo.squash = true;
732
228
733 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
734 tid,
735 fromIEW->mispredPC[tid],
736 fromIEW->squashedSeqNum[tid]);
229 // Send back the rob squashing signal so other stages know that the
230 // ROB is in the process of squashing.
231 toIEW->commitInfo.robSquashing = true;
737
232
738 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
739 tid,
740 fromIEW->nextPC[tid]);
233 toIEW->commitInfo.branchMispredict = fromIEW->branchMispredict;
741
234
742 commitStatus[tid] = ROBSquashing;
235 toIEW->commitInfo.branchTaken = fromIEW->branchTaken;
743
236
744 ++squashCounter;
237 toIEW->commitInfo.nextPC = fromIEW->nextPC;
745
238
746 // If we want to include the squashing instruction in the squash,
747 // then use one older sequence number.
748 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
239 toIEW->commitInfo.mispredPC = fromIEW->mispredPC;
749
240
750 if (fromIEW->includeSquashInst[tid] == true)
751 squashed_inst--;
752
753 // All younger instructions will be squashed. Set the sequence
754 // number as the youngest instruction in the ROB.
755 youngestSeqNum[tid] = squashed_inst;
756
757 rob->squash(squashed_inst, tid);
758 changedROBNumEntries[tid] = true;
759
760 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
761
762 toIEW->commitInfo[tid].squash = true;
763
764 // Send back the rob squashing signal so other stages know that
765 // the ROB is in the process of squashing.
766 toIEW->commitInfo[tid].robSquashing = true;
767
768 toIEW->commitInfo[tid].branchMispredict =
769 fromIEW->branchMispredict[tid];
770
771 toIEW->commitInfo[tid].branchTaken =
772 fromIEW->branchTaken[tid];
773
774 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
775
776 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
777
778 if (toIEW->commitInfo[tid].branchMispredict) {
779 ++branchMispredicts;
780 }
241 if (toIEW->commitInfo.branchMispredict) {
242 ++branchMispredicts;
781 }
243 }
782
783 }
784
244 }
245
785 setNextStatus();
786
787 if (squashCounter != numThreads) {
246 if (_status != ROBSquashing) {
788 // If we're not currently squashing, then get instructions.
789 getInsts();
790
791 // Try to commit any instructions.
792 commitInsts();
793 }
794
247 // If we're not currently squashing, then get instructions.
248 getInsts();
249
250 // Try to commit any instructions.
251 commitInsts();
252 }
253
795 //Check for any activity
796 threads = (*activeThreads).begin();
797
798 while (threads != (*activeThreads).end()) {
799 unsigned tid = *threads++;
800
801 if (changedROBNumEntries[tid]) {
802 toIEW->commitInfo[tid].usedROB = true;
803 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
804
805 if (rob->isEmpty(tid)) {
806 toIEW->commitInfo[tid].emptyROB = true;
807 }
808
809 wroteToTimeBuffer = true;
810 changedROBNumEntries[tid] = false;
811 }
254 // If the ROB is empty, we can set this stage to idle. Use this
255 // in the future when the Idle status will actually be utilized.
256#if 0
257 if (rob->isEmpty()) {
258 DPRINTF(Commit, "Commit: ROB is empty. Status changed to idle.\n");
259 _status = Idle;
260 // Schedule an event so that commit will actually wake up
261 // once something gets put in the ROB.
812 }
262 }
263#endif
813}
814
264}
265
266// Loop that goes through as many instructions in the ROB as possible and
267// tries to commit them. The actual work for committing is done by the
268// commitHead() function.
815template <class Impl>
816void
269template <class Impl>
270void
817DefaultCommit<Impl>::commitInsts()
271SimpleCommit<Impl>::commitInsts()
818{
819 ////////////////////////////////////
820 // Handle commit
272{
273 ////////////////////////////////////
274 // Handle commit
821 // Note that commit will be handled prior to putting new
822 // instructions in the ROB so that the ROB only tries to commit
823 // instructions it has in this current cycle, and not instructions
824 // it is writing in during this cycle. Can't commit and squash
825 // things at the same time...
275 // Note that commit will be handled prior to the ROB so that the ROB
276 // only tries to commit instructions it has in this current cycle, and
277 // not instructions it is writing in during this cycle.
278 // Can't commit and squash things at the same time...
826 ////////////////////////////////////
827
279 ////////////////////////////////////
280
828 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
281 if (rob->isEmpty())
282 return;
829
283
284 DynInstPtr head_inst = rob->readHeadInst();
285
830 unsigned num_committed = 0;
831
286 unsigned num_committed = 0;
287
832 DynInstPtr head_inst;
833
834 // Commit as many instructions as possible until the commit bandwidth
835 // limit is reached, or it becomes impossible to commit any more.
288 // Commit as many instructions as possible until the commit bandwidth
289 // limit is reached, or it becomes impossible to commit any more.
836 while (num_committed < commitWidth) {
837 int commit_thread = getCommittingThread();
290 while (!rob->isEmpty() &&
291 head_inst->readyToCommit() &&
292 num_committed < commitWidth)
293 {
294 DPRINTF(Commit, "Commit: Trying to commit head instruction.\n");
838
295
839 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
840 break;
841
842 head_inst = rob->readHeadInst(commit_thread);
843
844 int tid = head_inst->threadNumber;
845
846 assert(tid == commit_thread);
847
848 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
849 head_inst->seqNum, tid);
850
851 // If the head instruction is squashed, it is ready to retire
852 // (be removed from the ROB) at any time.
296 // If the head instruction is squashed, it is ready to retire at any
297 // time. However, we need to avoid updating any other state
298 // incorrectly if it's already been squashed.
853 if (head_inst->isSquashed()) {
854
299 if (head_inst->isSquashed()) {
300
855 DPRINTF(Commit, "Retiring squashed instruction from "
301 DPRINTF(Commit, "Commit: Retiring squashed instruction from "
856 "ROB.\n");
857
302 "ROB.\n");
303
858 rob->retireHead(commit_thread);
304 // Tell ROB to retire head instruction. This retires the head
305 // inst in the ROB without affecting any other stages.
306 rob->retireHead();
859
860 ++commitSquashedInsts;
861
307
308 ++commitSquashedInsts;
309
862 // Record that the number of ROB entries has changed.
863 changedROBNumEntries[tid] = true;
864 } else {
310 } else {
865 PC[tid] = head_inst->readPC();
866 nextPC[tid] = head_inst->readNextPC();
867
868 // Increment the total number of non-speculative instructions
869 // executed.
870 // Hack for now: it really shouldn't happen until after the
871 // commit is deemed to be successful, but this count is needed
872 // for syscalls.
311 // Increment the total number of non-speculative instructions
312 // executed.
313 // Hack for now: it really shouldn't happen until after the
314 // commit is deemed to be successful, but this count is needed
315 // for syscalls.
873 thread[tid]->funcExeInst++;
316 cpu->funcExeInst++;
874
875 // Try to commit the head instruction.
876 bool commit_success = commitHead(head_inst, num_committed);
877
317
318 // Try to commit the head instruction.
319 bool commit_success = commitHead(head_inst, num_committed);
320
321 // Update what instruction we are looking at if the commit worked.
878 if (commit_success) {
879 ++num_committed;
880
322 if (commit_success) {
323 ++num_committed;
324
881 changedROBNumEntries[tid] = true;
325 // Send back which instruction has been committed.
326 // @todo: Update this later when a wider pipeline is used.
327 // Hmm, can't really give a pointer here...perhaps the
328 // sequence number instead (copy).
329 toIEW->commitInfo.doneSeqNum = head_inst->seqNum;
882
330
883 // Set the doneSeqNum to the youngest committed instruction.
884 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
885
886 ++commitCommittedInsts;
887
331 ++commitCommittedInsts;
332
888 // To match the old model, don't count nops and instruction
889 // prefetches towards the total commit count.
890 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
891 cpu->instDone(tid);
333 if (!head_inst->isNop()) {
334 cpu->instDone();
892 }
335 }
893
894 PC[tid] = nextPC[tid];
895 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
896#if FULL_SYSTEM
897 int count = 0;
898 Addr oldpc;
899 do {
900 // Debug statement. Checks to make sure we're not
901 // currently updating state while handling PC events.
902 if (count == 0)
903 assert(!thread[tid]->inSyscall &&
904 !thread[tid]->trapPending);
905 oldpc = PC[tid];
906 cpu->system->pcEventQueue.service(
907 thread[tid]->getXCProxy());
908 count++;
909 } while (oldpc != PC[tid]);
910 if (count > 1) {
911 DPRINTF(Commit, "PC skip function event, stopping commit\n");
912 break;
913 }
914#endif
915 } else {
336 } else {
916 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
917 "[tid:%i] [sn:%i].\n",
918 head_inst->readPC(), tid ,head_inst->seqNum);
919 break;
920 }
921 }
337 break;
338 }
339 }
340
341 // Update the pointer to read the next instruction in the ROB.
342 head_inst = rob->readHeadInst();
922 }
923
924 DPRINTF(CommitRate, "%i\n", num_committed);
343 }
344
345 DPRINTF(CommitRate, "%i\n", num_committed);
925 numCommittedDist.sample(num_committed);
926
927 if (num_committed == commitWidth) {
928 commitEligible[0]++;
929 }
346 n_committed_dist.sample(num_committed);
930}
931
932template <class Impl>
933bool
347}
348
349template <class Impl>
350bool
934DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
351SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
935{
352{
353 // Make sure instruction is valid
936 assert(head_inst);
937
354 assert(head_inst);
355
938 int tid = head_inst->threadNumber;
939
940 // If the instruction is not executed yet, then it will need extra
941 // handling. Signal backwards that it should be executed.
356 // If the instruction is not executed yet, then it is a non-speculative
357 // or store inst. Signal backwards that it should be executed.
942 if (!head_inst->isExecuted()) {
943 // Keep this number correct. We have not yet actually executed
944 // and committed this instruction.
358 if (!head_inst->isExecuted()) {
359 // Keep this number correct. We have not yet actually executed
360 // and committed this instruction.
945 thread[tid]->funcExeInst--;
361 cpu->funcExeInst--;
946
362
947 head_inst->reachedCommit = true;
363 if (head_inst->isNonSpeculative()) {
364 DPRINTF(Commit, "Commit: Encountered a store or non-speculative "
365 "instruction at the head of the ROB, PC %#x.\n",
366 head_inst->readPC());
948
367
949 if (head_inst->isNonSpeculative() ||
950 head_inst->isMemBarrier() ||
951 head_inst->isWriteBarrier()) {
368 toIEW->commitInfo.nonSpecSeqNum = head_inst->seqNum;
952
369
953 DPRINTF(Commit, "Encountered a barrier or non-speculative "
954 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
955 head_inst->seqNum, head_inst->readPC());
956
957#if !FULL_SYSTEM
958 // Hack to make sure syscalls/memory barriers/quiesces
959 // aren't executed until all stores write back their data.
960 // This direct communication shouldn't be used for
961 // anything other than this.
962 if (inst_num > 0 || iewStage->hasStoresToWB())
963#else
964 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
965 head_inst->isQuiesce()) &&
966 iewStage->hasStoresToWB())
967#endif
968 {
969 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
970 return false;
971 }
972
973 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
974
975 // Change the instruction so it won't try to commit again until
976 // it is executed.
977 head_inst->clearCanCommit();
978
979 ++commitNonSpecStalls;
980
981 return false;
370 // Change the instruction so it won't try to commit again until
371 // it is executed.
372 head_inst->clearCanCommit();
373
374 ++commitNonSpecStalls;
375
376 return false;
982 } else if (head_inst->isLoad()) {
983 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
984 head_inst->seqNum, head_inst->readPC());
985
986 // Send back the non-speculative instruction's sequence
987 // number. Tell the lsq to re-execute the load.
988 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
989 toIEW->commitInfo[tid].uncached = true;
990 toIEW->commitInfo[tid].uncachedLoad = head_inst;
991
992 head_inst->clearCanCommit();
993
994 return false;
995 } else {
377 } else {
996 panic("Trying to commit un-executed instruction "
378 panic("Commit: Trying to commit un-executed instruction "
997 "of unknown type!\n");
998 }
999 }
1000
379 "of unknown type!\n");
380 }
381 }
382
1001 if (head_inst->isThreadSync()) {
1002 // Not handled for now.
1003 panic("Thread sync instructions are not handled yet.\n");
383 // Now check if it's one of the special trap or barrier or
384 // serializing instructions.
385 if (head_inst->isThreadSync() ||
386 head_inst->isSerializing() ||
387 head_inst->isMemBarrier() ||
388 head_inst->isWriteBarrier() )
389 {
390 // Not handled for now. Mem barriers and write barriers are safe
391 // to simply let commit as memory accesses only happen once they
392 // reach the head of commit. Not sure about the other two.
393 panic("Serializing or barrier instructions"
394 " are not handled yet.\n");
1004 }
1005
395 }
396
1006 // Stores mark themselves as completed.
1007 if (!head_inst->isStore()) {
1008 head_inst->setCompleted();
1009 }
1010
1011 // Use checker prior to updating anything due to traps or PC
1012 // based events.
1013 if (cpu->checker) {
1014 cpu->checker->tick(head_inst);
1015 }
1016
1017 // Check if the instruction caused a fault. If so, trap.
1018 Fault inst_fault = head_inst->getFault();
1019
1020 if (inst_fault != NoFault) {
397 // Check if the instruction caused a fault. If so, trap.
398 Fault inst_fault = head_inst->getFault();
399
400 if (inst_fault != NoFault) {
1021 head_inst->setCompleted();
401 if (!head_inst->isNop()) {
1022#if FULL_SYSTEM
402#if FULL_SYSTEM
1023 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1024 head_inst->seqNum, head_inst->readPC());
1025
1026 if (iewStage->hasStoresToWB() || inst_num > 0) {
1027 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1028 return false;
403 cpu->trap(inst_fault);
404#else // !FULL_SYSTEM
405 panic("fault (%d) detected @ PC %08p", inst_fault,
406 head_inst->PC);
407#endif // FULL_SYSTEM
1029 }
408 }
409 }
1030
410
1031 if (cpu->checker && head_inst->isStore()) {
1032 cpu->checker->tick(head_inst);
1033 }
411 // Check if we're really ready to commit. If not then return false.
412 // I'm pretty sure all instructions should be able to commit if they've
413 // reached this far. For now leave this in as a check.
414 if (!rob->isHeadReady()) {
415 panic("Commit: Unable to commit head instruction!\n");
416 return false;
417 }
1034
418
1035 assert(!thread[tid]->inSyscall);
419 // If it's a branch, then send back branch prediction update info
420 // to the fetch stage.
421 // This should be handled in the iew stage if a mispredict happens...
1036
422
1037 // Mark that we're in state update mode so that the trap's
1038 // execution doesn't generate extra squashes.
1039 thread[tid]->inSyscall = true;
423 if (head_inst->isControl()) {
1040
424
1041 // DTB will sometimes need the machine instruction for when
1042 // faults happen. So we will set it here, prior to the DTB
1043 // possibly needing it for its fault.
1044 thread[tid]->setInst(
1045 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
425#if 0
426 toIEW->nextPC = head_inst->readPC();
427 //Maybe switch over to BTB incorrect.
428 toIEW->btbMissed = head_inst->btbMiss();
429 toIEW->target = head_inst->nextPC;
430 //Maybe also include global history information.
431 //This simple version will have no branch prediction however.
432#endif
1046
433
1047 // Execute the trap. Although it's slightly unrealistic in
1048 // terms of timing (as it doesn't wait for the full timing of
1049 // the trap event to complete before updating state), it's
1050 // needed to update the state as soon as possible. This
1051 // prevents external agents from changing any specific state
1052 // that the trap need.
1053 cpu->trap(inst_fault, tid);
1054
1055 // Exit state update mode to avoid accidental updating.
1056 thread[tid]->inSyscall = false;
1057
1058 commitStatus[tid] = TrapPending;
1059
1060 // Generate trap squash event.
1061 generateTrapEvent(tid);
1062
1063 return false;
1064#else // !FULL_SYSTEM
1065 panic("fault (%d) detected @ PC %08p", inst_fault,
1066 head_inst->PC);
1067#endif // FULL_SYSTEM
434 ++commitCommittedBranches;
1068 }
1069
435 }
436
1070 updateComInstStats(head_inst);
1071
437 // Now that the instruction is going to be committed, finalize its
438 // trace data.
1072 if (head_inst->traceData) {
439 if (head_inst->traceData) {
1073 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1074 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1075 head_inst->traceData->finalize();
440 head_inst->traceData->finalize();
1076 head_inst->traceData = NULL;
1077 }
1078
441 }
442
1079 // Update the commit rename map
1080 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1081 renameMap[tid]->setEntry(head_inst->destRegIdx(i),
1082 head_inst->renamedDestRegIdx(i));
1083 }
443 //Finally clear the head ROB entry.
444 rob->retireHead();
1084
445
1085 // Finally clear the head ROB entry.
1086 rob->retireHead(tid);
1087
1088 // Return true to indicate that we have committed an instruction.
1089 return true;
1090}
1091
1092template <class Impl>
1093void
446 // Return true to indicate that we have committed an instruction.
447 return true;
448}
449
450template <class Impl>
451void
1094DefaultCommit<Impl>::getInsts()
452SimpleCommit<Impl>::getInsts()
1095{
453{
1096 // Read any renamed instructions and place them into the ROB.
454 //////////////////////////////////////
455 // Handle ROB functions
456 //////////////////////////////////////
457
458 // Read any issued instructions and place them into the ROB. Do this
459 // prior to squashing to avoid having instructions in the ROB that
460 // don't get squashed properly.
1097 int insts_to_process = min((int)renameWidth, fromRename->size);
1098
461 int insts_to_process = min((int)renameWidth, fromRename->size);
462
1099 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num)
463 for (int inst_num = 0;
464 inst_num < insts_to_process;
465 ++inst_num)
1100 {
466 {
1101 DynInstPtr inst = fromRename->insts[inst_num];
1102 int tid = inst->threadNumber;
1103
1104 if (!inst->isSquashed() &&
1105 commitStatus[tid] != ROBSquashing) {
1106 changedROBNumEntries[tid] = true;
1107
1108 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1109 inst->readPC(), inst->seqNum, tid);
1110
1111 rob->insertInst(inst);
1112
1113 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1114
1115 youngestSeqNum[tid] = inst->seqNum;
467 if (!fromRename->insts[inst_num]->isSquashed()) {
468 DPRINTF(Commit, "Commit: Inserting PC %#x into ROB.\n",
469 fromRename->insts[inst_num]->readPC());
470 rob->insertInst(fromRename->insts[inst_num]);
1116 } else {
471 } else {
1117 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
472 DPRINTF(Commit, "Commit: Instruction %i PC %#x was "
1118 "squashed, skipping.\n",
473 "squashed, skipping.\n",
1119 inst->readPC(), inst->seqNum, tid);
474 fromRename->insts[inst_num]->seqNum,
475 fromRename->insts[inst_num]->readPC());
1120 }
1121 }
1122}
1123
1124template <class Impl>
1125void
476 }
477 }
478}
479
480template <class Impl>
481void
1126DefaultCommit<Impl>::markCompletedInsts()
482SimpleCommit<Impl>::markCompletedInsts()
1127{
1128 // Grab completed insts out of the IEW instruction queue, and mark
1129 // instructions completed within the ROB.
1130 for (int inst_num = 0;
1131 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1132 ++inst_num)
1133 {
483{
484 // Grab completed insts out of the IEW instruction queue, and mark
485 // instructions completed within the ROB.
486 for (int inst_num = 0;
487 inst_num < fromIEW->size && fromIEW->insts[inst_num];
488 ++inst_num)
489 {
1134 if (!fromIEW->insts[inst_num]->isSquashed()) {
1135 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1136 "within ROB.\n",
1137 fromIEW->insts[inst_num]->threadNumber,
1138 fromIEW->insts[inst_num]->readPC(),
1139 fromIEW->insts[inst_num]->seqNum);
490 DPRINTF(Commit, "Commit: Marking PC %#x, SN %i ready within ROB.\n",
491 fromIEW->insts[inst_num]->readPC(),
492 fromIEW->insts[inst_num]->seqNum);
1140
493
1141 // Mark the instruction as ready to commit.
1142 fromIEW->insts[inst_num]->setCanCommit();
1143 }
494 // Mark the instruction as ready to commit.
495 fromIEW->insts[inst_num]->setCanCommit();
1144 }
1145}
1146
1147template <class Impl>
496 }
497}
498
499template <class Impl>
1148bool
1149DefaultCommit<Impl>::robDoneSquashing()
500uint64_t
501SimpleCommit<Impl>::readCommitPC()
1150{
502{
1151 list<unsigned>::iterator threads = (*activeThreads).begin();
1152
1153 while (threads != (*activeThreads).end()) {
1154 unsigned tid = *threads++;
1155
1156 if (!rob->isDoneSquashing(tid))
1157 return false;
1158 }
1159
1160 return true;
503 return rob->readHeadPC();
1161}
504}
1162
1163template <class Impl>
1164void
1165DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1166{
1167 unsigned thread = inst->threadNumber;
1168
1169 //
1170 // Pick off the software prefetches
1171 //
1172#ifdef TARGET_ALPHA
1173 if (inst->isDataPrefetch()) {
1174 statComSwp[thread]++;
1175 } else {
1176 statComInst[thread]++;
1177 }
1178#else
1179 statComInst[thread]++;
1180#endif
1181
1182 //
1183 // Control Instructions
1184 //
1185 if (inst->isControl())
1186 statComBranches[thread]++;
1187
1188 //
1189 // Memory references
1190 //
1191 if (inst->isMemRef()) {
1192 statComRefs[thread]++;
1193
1194 if (inst->isLoad()) {
1195 statComLoads[thread]++;
1196 }
1197 }
1198
1199 if (inst->isMemBarrier()) {
1200 statComMembars[thread]++;
1201 }
1202}
1203
1204////////////////////////////////////////
1205// //
1206// SMT COMMIT POLICY MAINTAINED HERE //
1207// //
1208////////////////////////////////////////
1209template <class Impl>
1210int
1211DefaultCommit<Impl>::getCommittingThread()
1212{
1213 if (numThreads > 1) {
1214 switch (commitPolicy) {
1215
1216 case Aggressive:
1217 //If Policy is Aggressive, commit will call
1218 //this function multiple times per
1219 //cycle
1220 return oldestReady();
1221
1222 case RoundRobin:
1223 return roundRobin();
1224
1225 case OldestReady:
1226 return oldestReady();
1227
1228 default:
1229 return -1;
1230 }
1231 } else {
1232 int tid = (*activeThreads).front();
1233
1234 if (commitStatus[tid] == Running ||
1235 commitStatus[tid] == Idle ||
1236 commitStatus[tid] == FetchTrapPending) {
1237 return tid;
1238 } else {
1239 return -1;
1240 }
1241 }
1242}
1243
1244template<class Impl>
1245int
1246DefaultCommit<Impl>::roundRobin()
1247{
1248 list<unsigned>::iterator pri_iter = priority_list.begin();
1249 list<unsigned>::iterator end = priority_list.end();
1250
1251 while (pri_iter != end) {
1252 unsigned tid = *pri_iter;
1253
1254 if (commitStatus[tid] == Running ||
1255 commitStatus[tid] == Idle) {
1256
1257 if (rob->isHeadReady(tid)) {
1258 priority_list.erase(pri_iter);
1259 priority_list.push_back(tid);
1260
1261 return tid;
1262 }
1263 }
1264
1265 pri_iter++;
1266 }
1267
1268 return -1;
1269}
1270
1271template<class Impl>
1272int
1273DefaultCommit<Impl>::oldestReady()
1274{
1275 unsigned oldest = 0;
1276 bool first = true;
1277
1278 list<unsigned>::iterator threads = (*activeThreads).begin();
1279
1280 while (threads != (*activeThreads).end()) {
1281 unsigned tid = *threads++;
1282
1283 if (!rob->isEmpty(tid) &&
1284 (commitStatus[tid] == Running ||
1285 commitStatus[tid] == Idle ||
1286 commitStatus[tid] == FetchTrapPending)) {
1287
1288 if (rob->isHeadReady(tid)) {
1289
1290 DynInstPtr head_inst = rob->readHeadInst(tid);
1291
1292 if (first) {
1293 oldest = tid;
1294 first = false;
1295 } else if (head_inst->seqNum < oldest) {
1296 oldest = tid;
1297 }
1298 }
1299 }
1300 }
1301
1302 if (!first) {
1303 return oldest;
1304 } else {
1305 return -1;
1306 }
1307}