commit_impl.hh (12422:9d6162c8c1de) | commit_impl.hh (13429:a1e199fd8122) |
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1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2010-2014, 2017 ARM Limited 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 622 unchanged lines hidden (view full) --- 631 squashAfterInst[tid] = NULL; 632 633 commitStatus[tid] = ROBSquashing; 634 cpu->activityThisCycle(); 635} 636 637template <class Impl> 638void | 1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2010-2014, 2017 ARM Limited 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 622 unchanged lines hidden (view full) --- 631 squashAfterInst[tid] = NULL; 632 633 commitStatus[tid] = ROBSquashing; 634 cpu->activityThisCycle(); 635} 636 637template <class Impl> 638void |
639DefaultCommit | 639DefaultCommit<Impl>::squashAfter(ThreadID tid, const DynInstPtr &head_inst) |
640{ 641 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 642 tid, head_inst->seqNum); 643 644 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst); 645 commitStatus[tid] = SquashAfterPending; 646 squashAfterInst[tid] = head_inst; 647} --- 43 unchanged lines hidden (view full) --- 691 while (threads != end) { 692 ThreadID tid = *threads++; 693 694 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 695 // The ROB has more instructions it can commit. Its next status 696 // will be active. 697 _nextStatus = Active; 698 | 640{ 641 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 642 tid, head_inst->seqNum); 643 644 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst); 645 commitStatus[tid] = SquashAfterPending; 646 squashAfterInst[tid] = head_inst; 647} --- 43 unchanged lines hidden (view full) --- 691 while (threads != end) { 692 ThreadID tid = *threads++; 693 694 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 695 // The ROB has more instructions it can commit. Its next status 696 // will be active. 697 _nextStatus = Active; 698 |
699 DynInstPtr inst = rob->readHeadInst(tid); | 699 const DynInstPtr &inst M5_VAR_USED = rob->readHeadInst(tid); |
700 701 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 702 " ROB and ready to commit\n", 703 tid, inst->seqNum, inst->pcState()); 704 705 } else if (!rob->isEmpty(tid)) { | 700 701 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 702 " ROB and ready to commit\n", 703 tid, inst->seqNum, inst->pcState()); 704 705 } else if (!rob->isEmpty(tid)) { |
706 DynInstPtr inst = rob->readHeadInst(tid); | 706 const DynInstPtr &inst = rob->readHeadInst(tid); |
707 708 ppCommitStall->notify(inst); 709 710 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 711 "%s is head of ROB and not ready\n", 712 tid, inst->seqNum, inst->pcState()); 713 } 714 --- 416 unchanged lines hidden (view full) --- 1131 1132 if (num_committed == commitWidth) { 1133 commitEligibleSamples++; 1134 } 1135} 1136 1137template <class Impl> 1138bool | 707 708 ppCommitStall->notify(inst); 709 710 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 711 "%s is head of ROB and not ready\n", 712 tid, inst->seqNum, inst->pcState()); 713 } 714 --- 416 unchanged lines hidden (view full) --- 1131 1132 if (num_committed == commitWidth) { 1133 commitEligibleSamples++; 1134 } 1135} 1136 1137template <class Impl> 1138bool |
1139DefaultCommit | 1139DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num) |
1140{ 1141 assert(head_inst); 1142 1143 ThreadID tid = head_inst->threadNumber; 1144 1145 // If the instruction is not executed yet, then it will need extra 1146 // handling. Signal backwards that it should be executed. 1147 if (!head_inst->isExecuted()) { --- 164 unchanged lines hidden (view full) --- 1312DefaultCommit<Impl>::getInsts() 1313{ 1314 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1315 1316 // Read any renamed instructions and place them into the ROB. 1317 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1318 1319 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { | 1140{ 1141 assert(head_inst); 1142 1143 ThreadID tid = head_inst->threadNumber; 1144 1145 // If the instruction is not executed yet, then it will need extra 1146 // handling. Signal backwards that it should be executed. 1147 if (!head_inst->isExecuted()) { --- 164 unchanged lines hidden (view full) --- 1312DefaultCommit<Impl>::getInsts() 1313{ 1314 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1315 1316 // Read any renamed instructions and place them into the ROB. 1317 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1318 1319 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { |
1320 DynInstPtr inst; 1321 1322 inst = fromRename->insts[inst_num]; | 1320 const DynInstPtr &inst = fromRename->insts[inst_num]; |
1323 ThreadID tid = inst->threadNumber; 1324 1325 if (!inst->isSquashed() && 1326 commitStatus[tid] != ROBSquashing && 1327 commitStatus[tid] != TrapPending) { 1328 changedROBNumEntries[tid] = true; 1329 1330 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", --- 30 unchanged lines hidden (view full) --- 1361 // Mark the instruction as ready to commit. 1362 fromIEW->insts[inst_num]->setCanCommit(); 1363 } 1364 } 1365} 1366 1367template <class Impl> 1368void | 1321 ThreadID tid = inst->threadNumber; 1322 1323 if (!inst->isSquashed() && 1324 commitStatus[tid] != ROBSquashing && 1325 commitStatus[tid] != TrapPending) { 1326 changedROBNumEntries[tid] = true; 1327 1328 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", --- 30 unchanged lines hidden (view full) --- 1359 // Mark the instruction as ready to commit. 1360 fromIEW->insts[inst_num]->setCanCommit(); 1361 } 1362 } 1363} 1364 1365template <class Impl> 1366void |
1369DefaultCommit | 1367DefaultCommit<Impl>::updateComInstStats(const DynInstPtr &inst) |
1370{ 1371 ThreadID tid = inst->threadNumber; 1372 1373 if (!inst->isMicroop() || inst->isLastMicroop()) 1374 instsCommitted[tid]++; 1375 opsCommitted[tid]++; 1376 1377 // To match the old model, don't count nops and instruction --- 124 unchanged lines hidden (view full) --- 1502 1503 if (!rob->isEmpty(tid) && 1504 (commitStatus[tid] == Running || 1505 commitStatus[tid] == Idle || 1506 commitStatus[tid] == FetchTrapPending)) { 1507 1508 if (rob->isHeadReady(tid)) { 1509 | 1368{ 1369 ThreadID tid = inst->threadNumber; 1370 1371 if (!inst->isMicroop() || inst->isLastMicroop()) 1372 instsCommitted[tid]++; 1373 opsCommitted[tid]++; 1374 1375 // To match the old model, don't count nops and instruction --- 124 unchanged lines hidden (view full) --- 1500 1501 if (!rob->isEmpty(tid) && 1502 (commitStatus[tid] == Running || 1503 commitStatus[tid] == Idle || 1504 commitStatus[tid] == FetchTrapPending)) { 1505 1506 if (rob->isHeadReady(tid)) { 1507 |
1510 DynInstPtr head_inst = rob->readHeadInst(tid); | 1508 const DynInstPtr &head_inst = rob->readHeadInst(tid); |
1511 1512 if (first) { 1513 oldest = tid; 1514 first = false; 1515 } else if (head_inst->seqNum < oldest) { 1516 oldest = tid; 1517 } 1518 } 1519 } 1520 } 1521 1522 if (!first) { 1523 return oldest; 1524 } else { 1525 return InvalidThreadID; 1526 } 1527} 1528 1529#endif//__CPU_O3_COMMIT_IMPL_HH__ | 1509 1510 if (first) { 1511 oldest = tid; 1512 first = false; 1513 } else if (head_inst->seqNum < oldest) { 1514 oldest = tid; 1515 } 1516 } 1517 } 1518 } 1519 1520 if (!first) { 1521 return oldest; 1522 } else { 1523 return InvalidThreadID; 1524 } 1525} 1526 1527#endif//__CPU_O3_COMMIT_IMPL_HH__ |