commit_impl.hh (12127:4207df055b0d) commit_impl.hh (12216:70bb3ae0fbfc)
1/*
2 * Copyright 2014 Google, Inc.
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2010-2014 ARM Limited
3 * Copyright (c) 2010-2014, 2017 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated

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1039 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1040
1041 if (tid == 0) {
1042 canHandleInterrupts = (!head_inst->isDelayedCommit()) &&
1043 ((THE_ISA != ALPHA_ISA) ||
1044 (!(pc[0].instAddr() & 0x3)));
1045 }
1046
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated

--- 1027 unchanged lines hidden (view full) ---

1039 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1040
1041 if (tid == 0) {
1042 canHandleInterrupts = (!head_inst->isDelayedCommit()) &&
1043 ((THE_ISA != ALPHA_ISA) ||
1044 (!(pc[0].instAddr() & 0x3)));
1045 }
1046
1047 // at this point store conditionals should either have
1048 // been completed or predicated false
1049 assert(!head_inst->isStoreConditional() ||
1050 head_inst->isCompleted() ||
1051 !head_inst->readPredicate());
1052
1047 // Updates misc. registers.
1048 head_inst->updateMiscRegs();
1049
1050 // Check instruction execution if it successfully commits and
1051 // is not carrying a fault.
1052 if (cpu->checker) {
1053 cpu->checker->verify(head_inst);
1054 }

--- 466 unchanged lines hidden --- 		1053 // Updates misc. registers.
1054 head_inst->updateMiscRegs();
1055
1056 // Check instruction execution if it successfully commits and
1057 // is not carrying a fault.
1058 if (cpu->checker) {
1059 cpu->checker->verify(head_inst);
1060 }

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