1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "config/full_system.hh"
32#include "config/use_checker.hh"
33
34#include <algorithm>
35#include <string>
36
37#include "base/loader/symtab.hh"
38#include "base/timebuf.hh"
39#include "cpu/exetrace.hh"
40#include "cpu/o3/commit.hh"
41#include "cpu/o3/thread_state.hh"
42
43#if USE_CHECKER
44#include "cpu/checker/cpu.hh"
45#endif
46
47using namespace std;
48
49template <class Impl>
50DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
51 unsigned _tid)
52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
53{
54 this->setFlags(Event::AutoDelete);
55}
56
57template <class Impl>
58void
59DefaultCommit<Impl>::TrapEvent::process()
60{
61 // This will get reset by commit if it was switched out at the
62 // time of this event processing.
63 commit->trapSquash[tid] = true;
64}
65
66template <class Impl>
67const char *
68DefaultCommit<Impl>::TrapEvent::description()
69{
70 return "Trap event";
71}
72
73template <class Impl>
74DefaultCommit<Impl>::DefaultCommit(Params *params)
75 : squashCounter(0),
76 iewToCommitDelay(params->iewToCommitDelay),
77 commitToIEWDelay(params->commitToIEWDelay),
78 renameToROBDelay(params->renameToROBDelay),
79 fetchToCommitDelay(params->commitToFetchDelay),
80 renameWidth(params->renameWidth),
81 commitWidth(params->commitWidth),
82 numThreads(params->numberOfThreads),
83 drainPending(false),
84 switchedOut(false),
85 trapLatency(params->trapLatency),
86 fetchTrapLatency(params->fetchTrapLatency)
87{
88 _status = Active;
89 _nextStatus = Inactive;
90 string policy = params->smtCommitPolicy;
91
92 //Convert string to lowercase
93 std::transform(policy.begin(), policy.end(), policy.begin(),
94 (int(*)(int)) tolower);
95
96 //Assign commit policy
97 if (policy == "aggressive"){
98 commitPolicy = Aggressive;
99
100 DPRINTF(Commit,"Commit Policy set to Aggressive.");
101 } else if (policy == "roundrobin"){
102 commitPolicy = RoundRobin;
103
104 //Set-Up Priority List
105 for (int tid=0; tid < numThreads; tid++) {
106 priority_list.push_back(tid);
107 }
108
109 DPRINTF(Commit,"Commit Policy set to Round Robin.");
110 } else if (policy == "oldestready"){
111 commitPolicy = OldestReady;
112
113 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
114 } else {
115 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
116 "RoundRobin,OldestReady}");
117 }
118
119 for (int i=0; i < numThreads; i++) {
120 commitStatus[i] = Idle;
121 changedROBNumEntries[i] = false;
122 trapSquash[i] = false;
123 tcSquash[i] = false;
124 PC[i] = nextPC[i] = 0;
125 }
126
127 fetchFaultTick = 0;
128 fetchTrapWait = 0;
129}
130
131template <class Impl>
132std::string
133DefaultCommit<Impl>::name() const
134{
135 return cpu->name() + ".commit";
136}
137
138template <class Impl>
139void
140DefaultCommit<Impl>::regStats()
141{
142 using namespace Stats;
143 commitCommittedInsts
144 .name(name() + ".commitCommittedInsts")
145 .desc("The number of committed instructions")
146 .prereq(commitCommittedInsts);
147 commitSquashedInsts
148 .name(name() + ".commitSquashedInsts")
149 .desc("The number of squashed insts skipped by commit")
150 .prereq(commitSquashedInsts);
151 commitSquashEvents
152 .name(name() + ".commitSquashEvents")
153 .desc("The number of times commit is told to squash")
154 .prereq(commitSquashEvents);
155 commitNonSpecStalls
156 .name(name() + ".commitNonSpecStalls")
157 .desc("The number of times commit has been forced to stall to "
158 "communicate backwards")
159 .prereq(commitNonSpecStalls);
160 branchMispredicts
161 .name(name() + ".branchMispredicts")
162 .desc("The number of times a branch was mispredicted")
163 .prereq(branchMispredicts);
164 numCommittedDist
165 .init(0,commitWidth,1)
166 .name(name() + ".COM:committed_per_cycle")
167 .desc("Number of insts commited each cycle")
168 .flags(Stats::pdf)
169 ;
170
171 statComInst
172 .init(cpu->number_of_threads)
173 .name(name() + ".COM:count")
174 .desc("Number of instructions committed")
175 .flags(total)
176 ;
177
178 statComSwp
179 .init(cpu->number_of_threads)
180 .name(name() + ".COM:swp_count")
181 .desc("Number of s/w prefetches committed")
182 .flags(total)
183 ;
184
185 statComRefs
186 .init(cpu->number_of_threads)
187 .name(name() + ".COM:refs")
188 .desc("Number of memory references committed")
189 .flags(total)
190 ;
191
192 statComLoads
193 .init(cpu->number_of_threads)
194 .name(name() + ".COM:loads")
195 .desc("Number of loads committed")
196 .flags(total)
197 ;
198
199 statComMembars
200 .init(cpu->number_of_threads)
201 .name(name() + ".COM:membars")
202 .desc("Number of memory barriers committed")
203 .flags(total)
204 ;
205
206 statComBranches
207 .init(cpu->number_of_threads)
208 .name(name() + ".COM:branches")
209 .desc("Number of branches committed")
210 .flags(total)
211 ;
212
213 commitEligible
214 .init(cpu->number_of_threads)
215 .name(name() + ".COM:bw_limited")
216 .desc("number of insts not committed due to BW limits")
217 .flags(total)
218 ;
219
220 commitEligibleSamples
221 .name(name() + ".COM:bw_lim_events")
222 .desc("number cycles where commit BW limit reached")
223 ;
224}
225
226template <class Impl>
227void
228DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
229{
230 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
231 cpu = cpu_ptr;
232
233 // Commit must broadcast the number of free entries it has at the start of
234 // the simulation, so it starts as active.
235 cpu->activateStage(O3CPU::CommitIdx);
236
237 trapLatency = cpu->cycles(trapLatency);
238 fetchTrapLatency = cpu->cycles(fetchTrapLatency);
239}
240
241template <class Impl>
242void
243DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)
244{
245 thread = threads;
246}
247
248template <class Impl>
249void
250DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
251{
252 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
253 timeBuffer = tb_ptr;
254
255 // Setup wire to send information back to IEW.
256 toIEW = timeBuffer->getWire(0);
257
258 // Setup wire to read data from IEW (for the ROB).
259 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
260}
261
262template <class Impl>
263void
264DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
265{
266 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
267 fetchQueue = fq_ptr;
268
269 // Setup wire to get instructions from rename (for the ROB).
270 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
271}
272
273template <class Impl>
274void
275DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
276{
277 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
278 renameQueue = rq_ptr;
279
280 // Setup wire to get instructions from rename (for the ROB).
281 fromRename = renameQueue->getWire(-renameToROBDelay);
282}
283
284template <class Impl>
285void
286DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
287{
288 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
289 iewQueue = iq_ptr;
290
291 // Setup wire to get instructions from IEW.
292 fromIEW = iewQueue->getWire(-iewToCommitDelay);
293}
294
295template <class Impl>
296void
297DefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage)
298{
299 fetchStage = fetch_stage;
300}
301
302template <class Impl>
303void
304DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
305{
306 iewStage = iew_stage;
307}
308
309template<class Impl>
310void
311DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr)
312{
313 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
314 activeThreads = at_ptr;
315}
316
317template <class Impl>
318void
319DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
320{
321 DPRINTF(Commit, "Setting rename map pointers.\n");
322
323 for (int i=0; i < numThreads; i++) {
324 renameMap[i] = &rm_ptr[i];
325 }
326}
327
328template <class Impl>
329void
330DefaultCommit<Impl>::setROB(ROB *rob_ptr)
331{
332 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
333 rob = rob_ptr;
334}
335
336template <class Impl>
337void
338DefaultCommit<Impl>::initStage()
339{
340 rob->setActiveThreads(activeThreads);
341 rob->resetEntries();
342
343 // Broadcast the number of free entries.
344 for (int i=0; i < numThreads; i++) {
345 toIEW->commitInfo[i].usedROB = true;
346 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
347 }
348
349 cpu->activityThisCycle();
350}
351
352template <class Impl>
|
365}
366
367template <class Impl>
368void
369DefaultCommit<Impl>::switchOut()
370{
371 switchedOut = true;
372 drainPending = false;
373 rob->switchOut();
374}
375
376template <class Impl>
377void
378DefaultCommit<Impl>::resume()
379{
380}
381
382template <class Impl>
383void
384DefaultCommit<Impl>::takeOverFrom()
385{
386 switchedOut = false;
387 _status = Active;
388 _nextStatus = Inactive;
389 for (int i=0; i < numThreads; i++) {
390 commitStatus[i] = Idle;
391 changedROBNumEntries[i] = false;
392 trapSquash[i] = false;
393 tcSquash[i] = false;
394 }
395 squashCounter = 0;
396 rob->takeOverFrom();
397}
398
399template <class Impl>
400void
401DefaultCommit<Impl>::updateStatus()
402{
403 // reset ROB changed variable
404 list<unsigned>::iterator threads = (*activeThreads).begin();
405 while (threads != (*activeThreads).end()) {
406 unsigned tid = *threads++;
407 changedROBNumEntries[tid] = false;
408
409 // Also check if any of the threads has a trap pending
410 if (commitStatus[tid] == TrapPending ||
411 commitStatus[tid] == FetchTrapPending) {
412 _nextStatus = Active;
413 }
414 }
415
416 if (_nextStatus == Inactive && _status == Active) {
417 DPRINTF(Activity, "Deactivating stage.\n");
418 cpu->deactivateStage(O3CPU::CommitIdx);
419 } else if (_nextStatus == Active && _status == Inactive) {
420 DPRINTF(Activity, "Activating stage.\n");
421 cpu->activateStage(O3CPU::CommitIdx);
422 }
423
424 _status = _nextStatus;
425}
426
427template <class Impl>
428void
429DefaultCommit<Impl>::setNextStatus()
430{
431 int squashes = 0;
432
433 list<unsigned>::iterator threads = (*activeThreads).begin();
434
435 while (threads != (*activeThreads).end()) {
436 unsigned tid = *threads++;
437
438 if (commitStatus[tid] == ROBSquashing) {
439 squashes++;
440 }
441 }
442
443 squashCounter = squashes;
444
445 // If commit is currently squashing, then it will have activity for the
446 // next cycle. Set its next status as active.
447 if (squashCounter) {
448 _nextStatus = Active;
449 }
450}
451
452template <class Impl>
453bool
454DefaultCommit<Impl>::changedROBEntries()
455{
456 list<unsigned>::iterator threads = (*activeThreads).begin();
457
458 while (threads != (*activeThreads).end()) {
459 unsigned tid = *threads++;
460
461 if (changedROBNumEntries[tid]) {
462 return true;
463 }
464 }
465
466 return false;
467}
468
469template <class Impl>
470unsigned
471DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
472{
473 return rob->numFreeEntries(tid);
474}
475
476template <class Impl>
477void
478DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
479{
480 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
481
482 TrapEvent *trap = new TrapEvent(this, tid);
483
484 trap->schedule(curTick + trapLatency);
485
486 thread[tid]->trapPending = true;
487}
488
489template <class Impl>
490void
491DefaultCommit<Impl>::generateTCEvent(unsigned tid)
492{
493 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
494
495 tcSquash[tid] = true;
496}
497
498template <class Impl>
499void
500DefaultCommit<Impl>::squashAll(unsigned tid)
501{
502 // If we want to include the squashing instruction in the squash,
503 // then use one older sequence number.
504 // Hopefully this doesn't mess things up. Basically I want to squash
505 // all instructions of this thread.
506 InstSeqNum squashed_inst = rob->isEmpty() ?
507 0 : rob->readHeadInst(tid)->seqNum - 1;;
508
509 // All younger instructions will be squashed. Set the sequence
510 // number as the youngest instruction in the ROB (0 in this case.
511 // Hopefully nothing breaks.)
512 youngestSeqNum[tid] = 0;
513
514 rob->squash(squashed_inst, tid);
515 changedROBNumEntries[tid] = true;
516
517 // Send back the sequence number of the squashed instruction.
518 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
519
520 // Send back the squash signal to tell stages that they should
521 // squash.
522 toIEW->commitInfo[tid].squash = true;
523
524 // Send back the rob squashing signal so other stages know that
525 // the ROB is in the process of squashing.
526 toIEW->commitInfo[tid].robSquashing = true;
527
528 toIEW->commitInfo[tid].branchMispredict = false;
529
530 toIEW->commitInfo[tid].nextPC = PC[tid];
531}
532
533template <class Impl>
534void
535DefaultCommit<Impl>::squashFromTrap(unsigned tid)
536{
537 squashAll(tid);
538
539 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
540
541 thread[tid]->trapPending = false;
542 thread[tid]->inSyscall = false;
543
544 trapSquash[tid] = false;
545
546 commitStatus[tid] = ROBSquashing;
547 cpu->activityThisCycle();
548}
549
550template <class Impl>
551void
552DefaultCommit<Impl>::squashFromTC(unsigned tid)
553{
554 squashAll(tid);
555
556 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
557
558 thread[tid]->inSyscall = false;
559 assert(!thread[tid]->trapPending);
560
561 commitStatus[tid] = ROBSquashing;
562 cpu->activityThisCycle();
563
564 tcSquash[tid] = false;
565}
566
567template <class Impl>
568void
569DefaultCommit<Impl>::tick()
570{
571 wroteToTimeBuffer = false;
572 _nextStatus = Inactive;
573
574 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
575 cpu->signalDrained();
576 drainPending = false;
577 return;
578 }
579
580 list<unsigned>::iterator threads = (*activeThreads).begin();
581
582 // Check if any of the threads are done squashing. Change the
583 // status if they are done.
584 while (threads != (*activeThreads).end()) {
585 unsigned tid = *threads++;
586
587 if (commitStatus[tid] == ROBSquashing) {
588
589 if (rob->isDoneSquashing(tid)) {
590 commitStatus[tid] = Running;
591 } else {
592 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
593 "insts this cycle.\n", tid);
594 rob->doSquash(tid);
595 toIEW->commitInfo[tid].robSquashing = true;
596 wroteToTimeBuffer = true;
597 }
598 }
599 }
600
601 commit();
602
603 markCompletedInsts();
604
605 threads = (*activeThreads).begin();
606
607 while (threads != (*activeThreads).end()) {
608 unsigned tid = *threads++;
609
610 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
611 // The ROB has more instructions it can commit. Its next status
612 // will be active.
613 _nextStatus = Active;
614
615 DynInstPtr inst = rob->readHeadInst(tid);
616
617 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
618 " ROB and ready to commit\n",
619 tid, inst->seqNum, inst->readPC());
620
621 } else if (!rob->isEmpty(tid)) {
622 DynInstPtr inst = rob->readHeadInst(tid);
623
624 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
625 "%#x is head of ROB and not ready\n",
626 tid, inst->seqNum, inst->readPC());
627 }
628
629 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
630 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
631 }
632
633
634 if (wroteToTimeBuffer) {
635 DPRINTF(Activity, "Activity This Cycle.\n");
636 cpu->activityThisCycle();
637 }
638
639 updateStatus();
640}
641
642template <class Impl>
643void
644DefaultCommit<Impl>::commit()
645{
646
647 //////////////////////////////////////
648 // Check for interrupts
649 //////////////////////////////////////
650
651#if FULL_SYSTEM
652 // Process interrupts if interrupts are enabled, not in PAL mode,
653 // and no other traps or external squashes are currently pending.
654 // @todo: Allow other threads to handle interrupts.
655 if (cpu->checkInterrupts &&
656 cpu->check_interrupts() &&
657 !cpu->inPalMode(readPC()) &&
658 !trapSquash[0] &&
659 !tcSquash[0]) {
660 // Tell fetch that there is an interrupt pending. This will
661 // make fetch wait until it sees a non PAL-mode PC, at which
662 // point it stops fetching instructions.
663 toIEW->commitInfo[0].interruptPending = true;
664
665 // Wait until the ROB is empty and all stores have drained in
666 // order to enter the interrupt.
667 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
668 // Not sure which thread should be the one to interrupt. For now
669 // always do thread 0.
670 assert(!thread[0]->inSyscall);
671 thread[0]->inSyscall = true;
672
673 // CPU will handle implementation of the interrupt.
674 cpu->processInterrupts();
675
676 // Now squash or record that I need to squash this cycle.
677 commitStatus[0] = TrapPending;
678
679 // Exit state update mode to avoid accidental updating.
680 thread[0]->inSyscall = false;
681
682 // Generate trap squash event.
683 generateTrapEvent(0);
684
685 toIEW->commitInfo[0].clearInterrupt = true;
686
687 DPRINTF(Commit, "Interrupt detected.\n");
688 } else {
689 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
690 }
691 }
692#endif // FULL_SYSTEM
693
694 ////////////////////////////////////
695 // Check for any possible squashes, handle them first
696 ////////////////////////////////////
697
698 list<unsigned>::iterator threads = (*activeThreads).begin();
699
700 while (threads != (*activeThreads).end()) {
701 unsigned tid = *threads++;
702
703 // Not sure which one takes priority. I think if we have
704 // both, that's a bad sign.
705 if (trapSquash[tid] == true) {
706 assert(!tcSquash[tid]);
707 squashFromTrap(tid);
708 } else if (tcSquash[tid] == true) {
709 squashFromTC(tid);
710 }
711
712 // Squashed sequence number must be older than youngest valid
713 // instruction in the ROB. This prevents squashes from younger
714 // instructions overriding squashes from older instructions.
715 if (fromIEW->squash[tid] &&
716 commitStatus[tid] != TrapPending &&
717 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
718
719 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
720 tid,
721 fromIEW->mispredPC[tid],
722 fromIEW->squashedSeqNum[tid]);
723
724 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
725 tid,
726 fromIEW->nextPC[tid]);
727
728 commitStatus[tid] = ROBSquashing;
729
730 // If we want to include the squashing instruction in the squash,
731 // then use one older sequence number.
732 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
733
734 if (fromIEW->includeSquashInst[tid] == true)
735 squashed_inst--;
736
737 // All younger instructions will be squashed. Set the sequence
738 // number as the youngest instruction in the ROB.
739 youngestSeqNum[tid] = squashed_inst;
740
741 rob->squash(squashed_inst, tid);
742 changedROBNumEntries[tid] = true;
743
744 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
745
746 toIEW->commitInfo[tid].squash = true;
747
748 // Send back the rob squashing signal so other stages know that
749 // the ROB is in the process of squashing.
750 toIEW->commitInfo[tid].robSquashing = true;
751
752 toIEW->commitInfo[tid].branchMispredict =
753 fromIEW->branchMispredict[tid];
754
755 toIEW->commitInfo[tid].branchTaken =
756 fromIEW->branchTaken[tid];
757
758 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
759
760 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
761
762 if (toIEW->commitInfo[tid].branchMispredict) {
763 ++branchMispredicts;
764 }
765 }
766
767 }
768
769 setNextStatus();
770
771 if (squashCounter != numThreads) {
772 // If we're not currently squashing, then get instructions.
773 getInsts();
774
775 // Try to commit any instructions.
776 commitInsts();
777 }
778
779 //Check for any activity
780 threads = (*activeThreads).begin();
781
782 while (threads != (*activeThreads).end()) {
783 unsigned tid = *threads++;
784
785 if (changedROBNumEntries[tid]) {
786 toIEW->commitInfo[tid].usedROB = true;
787 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
788
789 if (rob->isEmpty(tid)) {
790 toIEW->commitInfo[tid].emptyROB = true;
791 }
792
793 wroteToTimeBuffer = true;
794 changedROBNumEntries[tid] = false;
795 }
796 }
797}
798
799template <class Impl>
800void
801DefaultCommit<Impl>::commitInsts()
802{
803 ////////////////////////////////////
804 // Handle commit
805 // Note that commit will be handled prior to putting new
806 // instructions in the ROB so that the ROB only tries to commit
807 // instructions it has in this current cycle, and not instructions
808 // it is writing in during this cycle. Can't commit and squash
809 // things at the same time...
810 ////////////////////////////////////
811
812 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
813
814 unsigned num_committed = 0;
815
816 DynInstPtr head_inst;
817
818 // Commit as many instructions as possible until the commit bandwidth
819 // limit is reached, or it becomes impossible to commit any more.
820 while (num_committed < commitWidth) {
821 int commit_thread = getCommittingThread();
822
823 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
824 break;
825
826 head_inst = rob->readHeadInst(commit_thread);
827
828 int tid = head_inst->threadNumber;
829
830 assert(tid == commit_thread);
831
832 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
833 head_inst->seqNum, tid);
834
835 // If the head instruction is squashed, it is ready to retire
836 // (be removed from the ROB) at any time.
837 if (head_inst->isSquashed()) {
838
839 DPRINTF(Commit, "Retiring squashed instruction from "
840 "ROB.\n");
841
842 rob->retireHead(commit_thread);
843
844 ++commitSquashedInsts;
845
846 // Record that the number of ROB entries has changed.
847 changedROBNumEntries[tid] = true;
848 } else {
849 PC[tid] = head_inst->readPC();
850 nextPC[tid] = head_inst->readNextPC();
851
852 // Increment the total number of non-speculative instructions
853 // executed.
854 // Hack for now: it really shouldn't happen until after the
855 // commit is deemed to be successful, but this count is needed
856 // for syscalls.
857 thread[tid]->funcExeInst++;
858
859 // Try to commit the head instruction.
860 bool commit_success = commitHead(head_inst, num_committed);
861
862 if (commit_success) {
863 ++num_committed;
864
865 changedROBNumEntries[tid] = true;
866
867 // Set the doneSeqNum to the youngest committed instruction.
868 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
869
870 ++commitCommittedInsts;
871
872 // To match the old model, don't count nops and instruction
873 // prefetches towards the total commit count.
874 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
875 cpu->instDone(tid);
876 }
877
878 PC[tid] = nextPC[tid];
879 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
880#if FULL_SYSTEM
881 int count = 0;
882 Addr oldpc;
883 do {
884 // Debug statement. Checks to make sure we're not
885 // currently updating state while handling PC events.
886 if (count == 0)
887 assert(!thread[tid]->inSyscall &&
888 !thread[tid]->trapPending);
889 oldpc = PC[tid];
890 cpu->system->pcEventQueue.service(
891 thread[tid]->getTC());
892 count++;
893 } while (oldpc != PC[tid]);
894 if (count > 1) {
895 DPRINTF(Commit, "PC skip function event, stopping commit\n");
896 break;
897 }
898#endif
899 } else {
900 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
901 "[tid:%i] [sn:%i].\n",
902 head_inst->readPC(), tid ,head_inst->seqNum);
903 break;
904 }
905 }
906 }
907
908 DPRINTF(CommitRate, "%i\n", num_committed);
909 numCommittedDist.sample(num_committed);
910
911 if (num_committed == commitWidth) {
912 commitEligibleSamples++;
913 }
914}
915
916template <class Impl>
917bool
918DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
919{
920 assert(head_inst);
921
922 int tid = head_inst->threadNumber;
923
924 // If the instruction is not executed yet, then it will need extra
925 // handling. Signal backwards that it should be executed.
926 if (!head_inst->isExecuted()) {
927 // Keep this number correct. We have not yet actually executed
928 // and committed this instruction.
929 thread[tid]->funcExeInst--;
930
931 head_inst->setAtCommit();
932
933 if (head_inst->isNonSpeculative() ||
934 head_inst->isStoreConditional() ||
935 head_inst->isMemBarrier() ||
936 head_inst->isWriteBarrier()) {
937
938 DPRINTF(Commit, "Encountered a barrier or non-speculative "
939 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
940 head_inst->seqNum, head_inst->readPC());
941
942#if !FULL_SYSTEM
943 // Hack to make sure syscalls/memory barriers/quiesces
944 // aren't executed until all stores write back their data.
945 // This direct communication shouldn't be used for
946 // anything other than this.
947 if (inst_num > 0 || iewStage->hasStoresToWB())
948#else
949 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
950 head_inst->isQuiesce()) &&
951 iewStage->hasStoresToWB())
952#endif
953 {
954 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
955 return false;
956 }
957
958 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
959
960 // Change the instruction so it won't try to commit again until
961 // it is executed.
962 head_inst->clearCanCommit();
963
964 ++commitNonSpecStalls;
965
966 return false;
967 } else if (head_inst->isLoad()) {
968 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
969 head_inst->seqNum, head_inst->readPC());
970
971 // Send back the non-speculative instruction's sequence
972 // number. Tell the lsq to re-execute the load.
973 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
974 toIEW->commitInfo[tid].uncached = true;
975 toIEW->commitInfo[tid].uncachedLoad = head_inst;
976
977 head_inst->clearCanCommit();
978
979 return false;
980 } else {
981 panic("Trying to commit un-executed instruction "
982 "of unknown type!\n");
983 }
984 }
985
986 if (head_inst->isThreadSync()) {
987 // Not handled for now.
988 panic("Thread sync instructions are not handled yet.\n");
989 }
990
991 // Stores mark themselves as completed.
992 if (!head_inst->isStore()) {
993 head_inst->setCompleted();
994 }
995
996#if USE_CHECKER
997 // Use checker prior to updating anything due to traps or PC
998 // based events.
999 if (cpu->checker) {
1000 cpu->checker->verify(head_inst);
1001 }
1002#endif
1003
1004 // Check if the instruction caused a fault. If so, trap.
1005 Fault inst_fault = head_inst->getFault();
1006
1007 if (inst_fault != NoFault) {
1008 head_inst->setCompleted();
1009 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1010 head_inst->seqNum, head_inst->readPC());
1011
1012 if (iewStage->hasStoresToWB() || inst_num > 0) {
1013 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1014 return false;
1015 }
1016
1017#if USE_CHECKER
1018 if (cpu->checker && head_inst->isStore()) {
1019 cpu->checker->verify(head_inst);
1020 }
1021#endif
1022
1023 assert(!thread[tid]->inSyscall);
1024
1025 // Mark that we're in state update mode so that the trap's
1026 // execution doesn't generate extra squashes.
1027 thread[tid]->inSyscall = true;
1028
1029 // DTB will sometimes need the machine instruction for when
1030 // faults happen. So we will set it here, prior to the DTB
1031 // possibly needing it for its fault.
1032 thread[tid]->setInst(
1033 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1034
1035 // Execute the trap. Although it's slightly unrealistic in
1036 // terms of timing (as it doesn't wait for the full timing of
1037 // the trap event to complete before updating state), it's
1038 // needed to update the state as soon as possible. This
1039 // prevents external agents from changing any specific state
1040 // that the trap need.
1041 cpu->trap(inst_fault, tid);
1042
1043 // Exit state update mode to avoid accidental updating.
1044 thread[tid]->inSyscall = false;
1045
1046 commitStatus[tid] = TrapPending;
1047
1048 // Generate trap squash event.
1049 generateTrapEvent(tid);
1050
1051 return false;
1052 }
1053
1054 updateComInstStats(head_inst);
1055
1056 if (head_inst->traceData) {
1057 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1058 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1059 head_inst->traceData->finalize();
1060 head_inst->traceData = NULL;
1061 }
1062
1063 // Update the commit rename map
1064 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1065 renameMap[tid]->setEntry(head_inst->destRegIdx(i),
1066 head_inst->renamedDestRegIdx(i));
1067 }
1068
1069 // Finally clear the head ROB entry.
1070 rob->retireHead(tid);
1071
1072 // Return true to indicate that we have committed an instruction.
1073 return true;
1074}
1075
1076template <class Impl>
1077void
1078DefaultCommit<Impl>::getInsts()
1079{
1080 // Read any renamed instructions and place them into the ROB.
1081 int insts_to_process = min((int)renameWidth, fromRename->size);
1082
1083 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num)
1084 {
1085 DynInstPtr inst = fromRename->insts[inst_num];
1086 int tid = inst->threadNumber;
1087
1088 if (!inst->isSquashed() &&
1089 commitStatus[tid] != ROBSquashing) {
1090 changedROBNumEntries[tid] = true;
1091
1092 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1093 inst->readPC(), inst->seqNum, tid);
1094
1095 rob->insertInst(inst);
1096
1097 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1098
1099 youngestSeqNum[tid] = inst->seqNum;
1100 } else {
1101 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1102 "squashed, skipping.\n",
1103 inst->readPC(), inst->seqNum, tid);
1104 }
1105 }
1106}
1107
1108template <class Impl>
1109void
1110DefaultCommit<Impl>::markCompletedInsts()
1111{
1112 // Grab completed insts out of the IEW instruction queue, and mark
1113 // instructions completed within the ROB.
1114 for (int inst_num = 0;
1115 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1116 ++inst_num)
1117 {
1118 if (!fromIEW->insts[inst_num]->isSquashed()) {
1119 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1120 "within ROB.\n",
1121 fromIEW->insts[inst_num]->threadNumber,
1122 fromIEW->insts[inst_num]->readPC(),
1123 fromIEW->insts[inst_num]->seqNum);
1124
1125 // Mark the instruction as ready to commit.
1126 fromIEW->insts[inst_num]->setCanCommit();
1127 }
1128 }
1129}
1130
1131template <class Impl>
1132bool
1133DefaultCommit<Impl>::robDoneSquashing()
1134{
1135 list<unsigned>::iterator threads = (*activeThreads).begin();
1136
1137 while (threads != (*activeThreads).end()) {
1138 unsigned tid = *threads++;
1139
1140 if (!rob->isDoneSquashing(tid))
1141 return false;
1142 }
1143
1144 return true;
1145}
1146
1147template <class Impl>
1148void
1149DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1150{
1151 unsigned thread = inst->threadNumber;
1152
1153 //
1154 // Pick off the software prefetches
1155 //
1156#ifdef TARGET_ALPHA
1157 if (inst->isDataPrefetch()) {
1158 statComSwp[thread]++;
1159 } else {
1160 statComInst[thread]++;
1161 }
1162#else
1163 statComInst[thread]++;
1164#endif
1165
1166 //
1167 // Control Instructions
1168 //
1169 if (inst->isControl())
1170 statComBranches[thread]++;
1171
1172 //
1173 // Memory references
1174 //
1175 if (inst->isMemRef()) {
1176 statComRefs[thread]++;
1177
1178 if (inst->isLoad()) {
1179 statComLoads[thread]++;
1180 }
1181 }
1182
1183 if (inst->isMemBarrier()) {
1184 statComMembars[thread]++;
1185 }
1186}
1187
1188////////////////////////////////////////
1189// //
1190// SMT COMMIT POLICY MAINTAINED HERE //
1191// //
1192////////////////////////////////////////
1193template <class Impl>
1194int
1195DefaultCommit<Impl>::getCommittingThread()
1196{
1197 if (numThreads > 1) {
1198 switch (commitPolicy) {
1199
1200 case Aggressive:
1201 //If Policy is Aggressive, commit will call
1202 //this function multiple times per
1203 //cycle
1204 return oldestReady();
1205
1206 case RoundRobin:
1207 return roundRobin();
1208
1209 case OldestReady:
1210 return oldestReady();
1211
1212 default:
1213 return -1;
1214 }
1215 } else {
1216 int tid = (*activeThreads).front();
1217
1218 if (commitStatus[tid] == Running ||
1219 commitStatus[tid] == Idle ||
1220 commitStatus[tid] == FetchTrapPending) {
1221 return tid;
1222 } else {
1223 return -1;
1224 }
1225 }
1226}
1227
1228template<class Impl>
1229int
1230DefaultCommit<Impl>::roundRobin()
1231{
1232 list<unsigned>::iterator pri_iter = priority_list.begin();
1233 list<unsigned>::iterator end = priority_list.end();
1234
1235 while (pri_iter != end) {
1236 unsigned tid = *pri_iter;
1237
1238 if (commitStatus[tid] == Running ||
1239 commitStatus[tid] == Idle ||
1240 commitStatus[tid] == FetchTrapPending) {
1241
1242 if (rob->isHeadReady(tid)) {
1243 priority_list.erase(pri_iter);
1244 priority_list.push_back(tid);
1245
1246 return tid;
1247 }
1248 }
1249
1250 pri_iter++;
1251 }
1252
1253 return -1;
1254}
1255
1256template<class Impl>
1257int
1258DefaultCommit<Impl>::oldestReady()
1259{
1260 unsigned oldest = 0;
1261 bool first = true;
1262
1263 list<unsigned>::iterator threads = (*activeThreads).begin();
1264
1265 while (threads != (*activeThreads).end()) {
1266 unsigned tid = *threads++;
1267
1268 if (!rob->isEmpty(tid) &&
1269 (commitStatus[tid] == Running ||
1270 commitStatus[tid] == Idle ||
1271 commitStatus[tid] == FetchTrapPending)) {
1272
1273 if (rob->isHeadReady(tid)) {
1274
1275 DynInstPtr head_inst = rob->readHeadInst(tid);
1276
1277 if (first) {
1278 oldest = tid;
1279 first = false;
1280 } else if (head_inst->seqNum < oldest) {
1281 oldest = tid;
1282 }
1283 }
1284 }
1285 }
1286
1287 if (!first) {
1288 return oldest;
1289 } else {
1290 return -1;
1291 }
1292}
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