1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <algorithm>
32#include <string>
33
34#include "base/loader/symtab.hh"
35#include "base/timebuf.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/commit.hh"
39#include "cpu/o3/thread_state.hh"
40
41using namespace std;
42
43template <class Impl>
44DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
45 unsigned _tid)
46 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
47{
48 this->setFlags(Event::AutoDelete);
49}
50
51template <class Impl>
52void
53DefaultCommit<Impl>::TrapEvent::process()
54{
55 // This will get reset by commit if it was switched out at the
56 // time of this event processing.
57 commit->trapSquash[tid] = true;
58}
59
60template <class Impl>
61const char *
62DefaultCommit<Impl>::TrapEvent::description()
63{
64 return "Trap event";
65}
66
67template <class Impl>
68DefaultCommit<Impl>::DefaultCommit(Params *params)
69 : squashCounter(0),
70 iewToCommitDelay(params->iewToCommitDelay),
71 commitToIEWDelay(params->commitToIEWDelay),
72 renameToROBDelay(params->renameToROBDelay),
73 fetchToCommitDelay(params->commitToFetchDelay),
74 renameWidth(params->renameWidth),
75 commitWidth(params->commitWidth),
76 numThreads(params->numberOfThreads),
77 switchPending(false),
78 switchedOut(false),
79 trapLatency(params->trapLatency),
80 fetchTrapLatency(params->fetchTrapLatency)
81{
82 _status = Active;
83 _nextStatus = Inactive;
84 string policy = params->smtCommitPolicy;
85
86 //Convert string to lowercase
87 std::transform(policy.begin(), policy.end(), policy.begin(),
88 (int(*)(int)) tolower);
89
90 //Assign commit policy
91 if (policy == "aggressive"){
92 commitPolicy = Aggressive;
93
94 DPRINTF(Commit,"Commit Policy set to Aggressive.");
95 } else if (policy == "roundrobin"){
96 commitPolicy = RoundRobin;
97
98 //Set-Up Priority List
99 for (int tid=0; tid < numThreads; tid++) {
100 priority_list.push_back(tid);
101 }
102
103 DPRINTF(Commit,"Commit Policy set to Round Robin.");
104 } else if (policy == "oldestready"){
105 commitPolicy = OldestReady;
106
107 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
108 } else {
109 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
110 "RoundRobin,OldestReady}");
111 }
112
113 for (int i=0; i < numThreads; i++) {
114 commitStatus[i] = Idle;
115 changedROBNumEntries[i] = false;
116 trapSquash[i] = false;
117 tcSquash[i] = false;
118 PC[i] = nextPC[i] = 0;
119 }
120
121 fetchFaultTick = 0;
122 fetchTrapWait = 0;
123}
124
125template <class Impl>
126std::string
127DefaultCommit<Impl>::name() const
128{
129 return cpu->name() + ".commit";
130}
131
132template <class Impl>
133void
134DefaultCommit<Impl>::regStats()
135{
136 using namespace Stats;
137 commitCommittedInsts
138 .name(name() + ".commitCommittedInsts")
139 .desc("The number of committed instructions")
140 .prereq(commitCommittedInsts);
141 commitSquashedInsts
142 .name(name() + ".commitSquashedInsts")
143 .desc("The number of squashed insts skipped by commit")
144 .prereq(commitSquashedInsts);
145 commitSquashEvents
146 .name(name() + ".commitSquashEvents")
147 .desc("The number of times commit is told to squash")
148 .prereq(commitSquashEvents);
149 commitNonSpecStalls
150 .name(name() + ".commitNonSpecStalls")
151 .desc("The number of times commit has been forced to stall to "
152 "communicate backwards")
153 .prereq(commitNonSpecStalls);
154 branchMispredicts
155 .name(name() + ".branchMispredicts")
156 .desc("The number of times a branch was mispredicted")
157 .prereq(branchMispredicts);
158 numCommittedDist
159 .init(0,commitWidth,1)
160 .name(name() + ".COM:committed_per_cycle")
161 .desc("Number of insts commited each cycle")
162 .flags(Stats::pdf)
163 ;
164
165 statComInst
166 .init(cpu->number_of_threads)
167 .name(name() + ".COM:count")
168 .desc("Number of instructions committed")
169 .flags(total)
170 ;
171
172 statComSwp
173 .init(cpu->number_of_threads)
174 .name(name() + ".COM:swp_count")
175 .desc("Number of s/w prefetches committed")
176 .flags(total)
177 ;
178
179 statComRefs
180 .init(cpu->number_of_threads)
181 .name(name() + ".COM:refs")
182 .desc("Number of memory references committed")
183 .flags(total)
184 ;
185
186 statComLoads
187 .init(cpu->number_of_threads)
188 .name(name() + ".COM:loads")
189 .desc("Number of loads committed")
190 .flags(total)
191 ;
192
193 statComMembars
194 .init(cpu->number_of_threads)
195 .name(name() + ".COM:membars")
196 .desc("Number of memory barriers committed")
197 .flags(total)
198 ;
199
200 statComBranches
201 .init(cpu->number_of_threads)
202 .name(name() + ".COM:branches")
203 .desc("Number of branches committed")
204 .flags(total)
205 ;
206
207 //
208 // Commit-Eligible instructions...
209 //
210 // -> The number of instructions eligible to commit in those
211 // cycles where we reached our commit BW limit (less the number
212 // actually committed)
213 //
214 // -> The average value is computed over ALL CYCLES... not just
215 // the BW limited cycles
216 //
217 // -> The standard deviation is computed only over cycles where
218 // we reached the BW limit
219 //
207 commitEligible
208 .init(cpu->number_of_threads)
209 .name(name() + ".COM:bw_limited")
210 .desc("number of insts not committed due to BW limits")
211 .flags(total)
212 ;
213
214 commitEligibleSamples
215 .name(name() + ".COM:bw_lim_events")
216 .desc("number cycles where commit BW limit reached")
217 ;
218}
219
220template <class Impl>
221void
222DefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr)
223{
224 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
225 cpu = cpu_ptr;
226
227 // Commit must broadcast the number of free entries it has at the start of
228 // the simulation, so it starts as active.
229 cpu->activateStage(FullCPU::CommitIdx);
230
231 trapLatency = cpu->cycles(trapLatency);
232 fetchTrapLatency = cpu->cycles(fetchTrapLatency);
233}
234
235template <class Impl>
236void
237DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)
238{
239 thread = threads;
240}
241
242template <class Impl>
243void
244DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
245{
246 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
247 timeBuffer = tb_ptr;
248
249 // Setup wire to send information back to IEW.
250 toIEW = timeBuffer->getWire(0);
251
252 // Setup wire to read data from IEW (for the ROB).
253 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
254}
255
256template <class Impl>
257void
258DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
259{
260 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
261 fetchQueue = fq_ptr;
262
263 // Setup wire to get instructions from rename (for the ROB).
264 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
265}
266
267template <class Impl>
268void
269DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
270{
271 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
272 renameQueue = rq_ptr;
273
274 // Setup wire to get instructions from rename (for the ROB).
275 fromRename = renameQueue->getWire(-renameToROBDelay);
276}
277
278template <class Impl>
279void
280DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
281{
282 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
283 iewQueue = iq_ptr;
284
285 // Setup wire to get instructions from IEW.
286 fromIEW = iewQueue->getWire(-iewToCommitDelay);
287}
288
289template <class Impl>
290void
291DefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage)
292{
293 fetchStage = fetch_stage;
294}
295
296template <class Impl>
297void
298DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
299{
300 iewStage = iew_stage;
301}
302
303template<class Impl>
304void
305DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr)
306{
307 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
308 activeThreads = at_ptr;
309}
310
311template <class Impl>
312void
313DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
314{
315 DPRINTF(Commit, "Setting rename map pointers.\n");
316
317 for (int i=0; i < numThreads; i++) {
318 renameMap[i] = &rm_ptr[i];
319 }
320}
321
322template <class Impl>
323void
324DefaultCommit<Impl>::setROB(ROB *rob_ptr)
325{
326 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
327 rob = rob_ptr;
328}
329
330template <class Impl>
331void
332DefaultCommit<Impl>::initStage()
333{
334 rob->setActiveThreads(activeThreads);
335 rob->resetEntries();
336
337 // Broadcast the number of free entries.
338 for (int i=0; i < numThreads; i++) {
339 toIEW->commitInfo[i].usedROB = true;
340 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
341 }
342
343 cpu->activityThisCycle();
344}
345
346template <class Impl>
347void
348DefaultCommit<Impl>::switchOut()
349{
350 switchPending = true;
351}
352
353template <class Impl>
354void
355DefaultCommit<Impl>::doSwitchOut()
356{
357 switchedOut = true;
358 switchPending = false;
359 rob->switchOut();
360}
361
362template <class Impl>
363void
364DefaultCommit<Impl>::takeOverFrom()
365{
366 switchedOut = false;
367 _status = Active;
368 _nextStatus = Inactive;
369 for (int i=0; i < numThreads; i++) {
370 commitStatus[i] = Idle;
371 changedROBNumEntries[i] = false;
372 trapSquash[i] = false;
373 tcSquash[i] = false;
374 }
375 squashCounter = 0;
376 rob->takeOverFrom();
377}
378
379template <class Impl>
380void
381DefaultCommit<Impl>::updateStatus()
382{
383 // reset ROB changed variable
384 list<unsigned>::iterator threads = (*activeThreads).begin();
385 while (threads != (*activeThreads).end()) {
386 unsigned tid = *threads++;
387 changedROBNumEntries[tid] = false;
388
389 // Also check if any of the threads has a trap pending
390 if (commitStatus[tid] == TrapPending ||
391 commitStatus[tid] == FetchTrapPending) {
392 _nextStatus = Active;
393 }
394 }
395
396 if (_nextStatus == Inactive && _status == Active) {
397 DPRINTF(Activity, "Deactivating stage.\n");
398 cpu->deactivateStage(FullCPU::CommitIdx);
399 } else if (_nextStatus == Active && _status == Inactive) {
400 DPRINTF(Activity, "Activating stage.\n");
401 cpu->activateStage(FullCPU::CommitIdx);
402 }
403
404 _status = _nextStatus;
405}
406
407template <class Impl>
408void
409DefaultCommit<Impl>::setNextStatus()
410{
411 int squashes = 0;
412
413 list<unsigned>::iterator threads = (*activeThreads).begin();
414
415 while (threads != (*activeThreads).end()) {
416 unsigned tid = *threads++;
417
418 if (commitStatus[tid] == ROBSquashing) {
419 squashes++;
420 }
421 }
422
423 squashCounter = squashes;
424
425 // If commit is currently squashing, then it will have activity for the
426 // next cycle. Set its next status as active.
427 if (squashCounter) {
428 _nextStatus = Active;
429 }
430}
431
432template <class Impl>
433bool
434DefaultCommit<Impl>::changedROBEntries()
435{
436 list<unsigned>::iterator threads = (*activeThreads).begin();
437
438 while (threads != (*activeThreads).end()) {
439 unsigned tid = *threads++;
440
441 if (changedROBNumEntries[tid]) {
442 return true;
443 }
444 }
445
446 return false;
447}
448
449template <class Impl>
450unsigned
451DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
452{
453 return rob->numFreeEntries(tid);
454}
455
456template <class Impl>
457void
458DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
459{
460 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
461
462 TrapEvent *trap = new TrapEvent(this, tid);
463
464 trap->schedule(curTick + trapLatency);
465
466 thread[tid]->trapPending = true;
467}
468
469template <class Impl>
470void
471DefaultCommit<Impl>::generateTCEvent(unsigned tid)
472{
473 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
474
475 tcSquash[tid] = true;
476}
477
478template <class Impl>
479void
480DefaultCommit<Impl>::squashAll(unsigned tid)
481{
482 // If we want to include the squashing instruction in the squash,
483 // then use one older sequence number.
484 // Hopefully this doesn't mess things up. Basically I want to squash
485 // all instructions of this thread.
486 InstSeqNum squashed_inst = rob->isEmpty() ?
487 0 : rob->readHeadInst(tid)->seqNum - 1;;
488
489 // All younger instructions will be squashed. Set the sequence
490 // number as the youngest instruction in the ROB (0 in this case.
491 // Hopefully nothing breaks.)
492 youngestSeqNum[tid] = 0;
493
494 rob->squash(squashed_inst, tid);
495 changedROBNumEntries[tid] = true;
496
497 // Send back the sequence number of the squashed instruction.
498 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
499
500 // Send back the squash signal to tell stages that they should
501 // squash.
502 toIEW->commitInfo[tid].squash = true;
503
504 // Send back the rob squashing signal so other stages know that
505 // the ROB is in the process of squashing.
506 toIEW->commitInfo[tid].robSquashing = true;
507
508 toIEW->commitInfo[tid].branchMispredict = false;
509
510 toIEW->commitInfo[tid].nextPC = PC[tid];
511}
512
513template <class Impl>
514void
515DefaultCommit<Impl>::squashFromTrap(unsigned tid)
516{
517 squashAll(tid);
518
519 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
520
521 thread[tid]->trapPending = false;
522 thread[tid]->inSyscall = false;
523
524 trapSquash[tid] = false;
525
526 commitStatus[tid] = ROBSquashing;
527 cpu->activityThisCycle();
528}
529
530template <class Impl>
531void
532DefaultCommit<Impl>::squashFromTC(unsigned tid)
533{
534 squashAll(tid);
535
536 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
537
538 thread[tid]->inSyscall = false;
539 assert(!thread[tid]->trapPending);
540
541 commitStatus[tid] = ROBSquashing;
542 cpu->activityThisCycle();
543
544 tcSquash[tid] = false;
545}
546
547template <class Impl>
548void
549DefaultCommit<Impl>::tick()
550{
551 wroteToTimeBuffer = false;
552 _nextStatus = Inactive;
553
554 if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
555 cpu->signalSwitched();
556 return;
557 }
558
559 list<unsigned>::iterator threads = (*activeThreads).begin();
560
561 // Check if any of the threads are done squashing. Change the
562 // status if they are done.
563 while (threads != (*activeThreads).end()) {
564 unsigned tid = *threads++;
565
566 if (commitStatus[tid] == ROBSquashing) {
567
568 if (rob->isDoneSquashing(tid)) {
569 commitStatus[tid] = Running;
570 } else {
571 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
572 "insts this cycle.\n", tid);
573 rob->doSquash(tid);
574 toIEW->commitInfo[tid].robSquashing = true;
575 wroteToTimeBuffer = true;
576 }
577 }
578 }
579
580 commit();
581
582 markCompletedInsts();
583
584 threads = (*activeThreads).begin();
585
586 while (threads != (*activeThreads).end()) {
587 unsigned tid = *threads++;
588
589 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
590 // The ROB has more instructions it can commit. Its next status
591 // will be active.
592 _nextStatus = Active;
593
594 DynInstPtr inst = rob->readHeadInst(tid);
595
596 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
597 " ROB and ready to commit\n",
598 tid, inst->seqNum, inst->readPC());
599
600 } else if (!rob->isEmpty(tid)) {
601 DynInstPtr inst = rob->readHeadInst(tid);
602
603 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
604 "%#x is head of ROB and not ready\n",
605 tid, inst->seqNum, inst->readPC());
606 }
607
608 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
609 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
610 }
611
612
613 if (wroteToTimeBuffer) {
614 DPRINTF(Activity, "Activity This Cycle.\n");
615 cpu->activityThisCycle();
616 }
617
618 updateStatus();
619}
620
621template <class Impl>
622void
623DefaultCommit<Impl>::commit()
624{
625
626 //////////////////////////////////////
627 // Check for interrupts
628 //////////////////////////////////////
629
630#if FULL_SYSTEM
631 // Process interrupts if interrupts are enabled, not in PAL mode,
632 // and no other traps or external squashes are currently pending.
633 // @todo: Allow other threads to handle interrupts.
634 if (cpu->checkInterrupts &&
635 cpu->check_interrupts() &&
636 !cpu->inPalMode(readPC()) &&
637 !trapSquash[0] &&
638 !tcSquash[0]) {
639 // Tell fetch that there is an interrupt pending. This will
640 // make fetch wait until it sees a non PAL-mode PC, at which
641 // point it stops fetching instructions.
642 toIEW->commitInfo[0].interruptPending = true;
643
644 // Wait until the ROB is empty and all stores have drained in
645 // order to enter the interrupt.
646 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
647 // Not sure which thread should be the one to interrupt. For now
648 // always do thread 0.
649 assert(!thread[0]->inSyscall);
650 thread[0]->inSyscall = true;
651
652 // CPU will handle implementation of the interrupt.
653 cpu->processInterrupts();
654
655 // Now squash or record that I need to squash this cycle.
656 commitStatus[0] = TrapPending;
657
658 // Exit state update mode to avoid accidental updating.
659 thread[0]->inSyscall = false;
660
661 // Generate trap squash event.
662 generateTrapEvent(0);
663
664 toIEW->commitInfo[0].clearInterrupt = true;
665
666 DPRINTF(Commit, "Interrupt detected.\n");
667 } else {
668 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
669 }
670 }
671#endif // FULL_SYSTEM
672
673 ////////////////////////////////////
674 // Check for any possible squashes, handle them first
675 ////////////////////////////////////
676
677 list<unsigned>::iterator threads = (*activeThreads).begin();
678
679 while (threads != (*activeThreads).end()) {
680 unsigned tid = *threads++;
681
682 // Not sure which one takes priority. I think if we have
683 // both, that's a bad sign.
684 if (trapSquash[tid] == true) {
685 assert(!tcSquash[tid]);
686 squashFromTrap(tid);
687 } else if (tcSquash[tid] == true) {
688 squashFromTC(tid);
689 }
690
691 // Squashed sequence number must be older than youngest valid
692 // instruction in the ROB. This prevents squashes from younger
693 // instructions overriding squashes from older instructions.
694 if (fromIEW->squash[tid] &&
695 commitStatus[tid] != TrapPending &&
696 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
697
698 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
699 tid,
700 fromIEW->mispredPC[tid],
701 fromIEW->squashedSeqNum[tid]);
702
703 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
704 tid,
705 fromIEW->nextPC[tid]);
706
707 commitStatus[tid] = ROBSquashing;
708
709 // If we want to include the squashing instruction in the squash,
710 // then use one older sequence number.
711 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
712
713 if (fromIEW->includeSquashInst[tid] == true)
714 squashed_inst--;
715
716 // All younger instructions will be squashed. Set the sequence
717 // number as the youngest instruction in the ROB.
718 youngestSeqNum[tid] = squashed_inst;
719
720 rob->squash(squashed_inst, tid);
721 changedROBNumEntries[tid] = true;
722
723 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
724
725 toIEW->commitInfo[tid].squash = true;
726
727 // Send back the rob squashing signal so other stages know that
728 // the ROB is in the process of squashing.
729 toIEW->commitInfo[tid].robSquashing = true;
730
731 toIEW->commitInfo[tid].branchMispredict =
732 fromIEW->branchMispredict[tid];
733
734 toIEW->commitInfo[tid].branchTaken =
735 fromIEW->branchTaken[tid];
736
737 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
738
739 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
740
741 if (toIEW->commitInfo[tid].branchMispredict) {
742 ++branchMispredicts;
743 }
744 }
745
746 }
747
748 setNextStatus();
749
750 if (squashCounter != numThreads) {
751 // If we're not currently squashing, then get instructions.
752 getInsts();
753
754 // Try to commit any instructions.
755 commitInsts();
756 }
757
758 //Check for any activity
759 threads = (*activeThreads).begin();
760
761 while (threads != (*activeThreads).end()) {
762 unsigned tid = *threads++;
763
764 if (changedROBNumEntries[tid]) {
765 toIEW->commitInfo[tid].usedROB = true;
766 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
767
768 if (rob->isEmpty(tid)) {
769 toIEW->commitInfo[tid].emptyROB = true;
770 }
771
772 wroteToTimeBuffer = true;
773 changedROBNumEntries[tid] = false;
774 }
775 }
776}
777
778template <class Impl>
779void
780DefaultCommit<Impl>::commitInsts()
781{
782 ////////////////////////////////////
783 // Handle commit
784 // Note that commit will be handled prior to putting new
785 // instructions in the ROB so that the ROB only tries to commit
786 // instructions it has in this current cycle, and not instructions
787 // it is writing in during this cycle. Can't commit and squash
788 // things at the same time...
789 ////////////////////////////////////
790
791 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
792
793 unsigned num_committed = 0;
794
795 DynInstPtr head_inst;
796
797 // Commit as many instructions as possible until the commit bandwidth
798 // limit is reached, or it becomes impossible to commit any more.
799 while (num_committed < commitWidth) {
800 int commit_thread = getCommittingThread();
801
802 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
803 break;
804
805 head_inst = rob->readHeadInst(commit_thread);
806
807 int tid = head_inst->threadNumber;
808
809 assert(tid == commit_thread);
810
811 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
812 head_inst->seqNum, tid);
813
814 // If the head instruction is squashed, it is ready to retire
815 // (be removed from the ROB) at any time.
816 if (head_inst->isSquashed()) {
817
818 DPRINTF(Commit, "Retiring squashed instruction from "
819 "ROB.\n");
820
821 rob->retireHead(commit_thread);
822
823 ++commitSquashedInsts;
824
825 // Record that the number of ROB entries has changed.
826 changedROBNumEntries[tid] = true;
827 } else {
828 PC[tid] = head_inst->readPC();
829 nextPC[tid] = head_inst->readNextPC();
830
831 // Increment the total number of non-speculative instructions
832 // executed.
833 // Hack for now: it really shouldn't happen until after the
834 // commit is deemed to be successful, but this count is needed
835 // for syscalls.
836 thread[tid]->funcExeInst++;
837
838 // Try to commit the head instruction.
839 bool commit_success = commitHead(head_inst, num_committed);
840
841 if (commit_success) {
842 ++num_committed;
843
844 changedROBNumEntries[tid] = true;
845
846 // Set the doneSeqNum to the youngest committed instruction.
847 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
848
849 ++commitCommittedInsts;
850
851 // To match the old model, don't count nops and instruction
852 // prefetches towards the total commit count.
853 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
854 cpu->instDone(tid);
855 }
856
857 PC[tid] = nextPC[tid];
858 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
859#if FULL_SYSTEM
860 int count = 0;
861 Addr oldpc;
862 do {
863 // Debug statement. Checks to make sure we're not
864 // currently updating state while handling PC events.
865 if (count == 0)
866 assert(!thread[tid]->inSyscall &&
867 !thread[tid]->trapPending);
868 oldpc = PC[tid];
869 cpu->system->pcEventQueue.service(
870 thread[tid]->getTC());
871 count++;
872 } while (oldpc != PC[tid]);
873 if (count > 1) {
874 DPRINTF(Commit, "PC skip function event, stopping commit\n");
875 break;
876 }
877#endif
878 } else {
879 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
880 "[tid:%i] [sn:%i].\n",
881 head_inst->readPC(), tid ,head_inst->seqNum);
882 break;
883 }
884 }
885 }
886
887 DPRINTF(CommitRate, "%i\n", num_committed);
888 numCommittedDist.sample(num_committed);
889
890 if (num_committed == commitWidth) {
891 commitEligibleSamples++;
892 }
893}
894
895template <class Impl>
896bool
897DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
898{
899 assert(head_inst);
900
901 int tid = head_inst->threadNumber;
902
903 // If the instruction is not executed yet, then it will need extra
904 // handling. Signal backwards that it should be executed.
905 if (!head_inst->isExecuted()) {
906 // Keep this number correct. We have not yet actually executed
907 // and committed this instruction.
908 thread[tid]->funcExeInst--;
909
910 head_inst->reachedCommit = true;
911
912 if (head_inst->isNonSpeculative() ||
913 head_inst->isStoreConditional() ||
914 head_inst->isMemBarrier() ||
915 head_inst->isWriteBarrier()) {
916
917 DPRINTF(Commit, "Encountered a barrier or non-speculative "
918 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
919 head_inst->seqNum, head_inst->readPC());
920
921#if !FULL_SYSTEM
922 // Hack to make sure syscalls/memory barriers/quiesces
923 // aren't executed until all stores write back their data.
924 // This direct communication shouldn't be used for
925 // anything other than this.
926 if (inst_num > 0 || iewStage->hasStoresToWB())
927#else
928 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
929 head_inst->isQuiesce()) &&
930 iewStage->hasStoresToWB())
931#endif
932 {
933 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
934 return false;
935 }
936
937 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
938
939 // Change the instruction so it won't try to commit again until
940 // it is executed.
941 head_inst->clearCanCommit();
942
943 ++commitNonSpecStalls;
944
945 return false;
946 } else if (head_inst->isLoad()) {
947 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
948 head_inst->seqNum, head_inst->readPC());
949
950 // Send back the non-speculative instruction's sequence
951 // number. Tell the lsq to re-execute the load.
952 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
953 toIEW->commitInfo[tid].uncached = true;
954 toIEW->commitInfo[tid].uncachedLoad = head_inst;
955
956 head_inst->clearCanCommit();
957
958 return false;
959 } else {
960 panic("Trying to commit un-executed instruction "
961 "of unknown type!\n");
962 }
963 }
964
965 if (head_inst->isThreadSync()) {
966 // Not handled for now.
967 panic("Thread sync instructions are not handled yet.\n");
968 }
969
970 // Stores mark themselves as completed.
971 if (!head_inst->isStore()) {
972 head_inst->setCompleted();
973 }
974
975 // Use checker prior to updating anything due to traps or PC
976 // based events.
977 if (cpu->checker) {
978 cpu->checker->tick(head_inst);
979 }
980
981 // Check if the instruction caused a fault. If so, trap.
982 Fault inst_fault = head_inst->getFault();
983
984 if (inst_fault != NoFault) {
985 head_inst->setCompleted();
986#if FULL_SYSTEM
987 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
988 head_inst->seqNum, head_inst->readPC());
989
990 if (iewStage->hasStoresToWB() || inst_num > 0) {
991 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
992 return false;
993 }
994
995 if (cpu->checker && head_inst->isStore()) {
996 cpu->checker->tick(head_inst);
997 }
998
999 assert(!thread[tid]->inSyscall);
1000
1001 // Mark that we're in state update mode so that the trap's
1002 // execution doesn't generate extra squashes.
1003 thread[tid]->inSyscall = true;
1004
1005 // DTB will sometimes need the machine instruction for when
1006 // faults happen. So we will set it here, prior to the DTB
1007 // possibly needing it for its fault.
1008 thread[tid]->setInst(
1009 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1010
1011 // Execute the trap. Although it's slightly unrealistic in
1012 // terms of timing (as it doesn't wait for the full timing of
1013 // the trap event to complete before updating state), it's
1014 // needed to update the state as soon as possible. This
1015 // prevents external agents from changing any specific state
1016 // that the trap need.
1017 cpu->trap(inst_fault, tid);
1018
1019 // Exit state update mode to avoid accidental updating.
1020 thread[tid]->inSyscall = false;
1021
1022 commitStatus[tid] = TrapPending;
1023
1024 // Generate trap squash event.
1025 generateTrapEvent(tid);
1026
1027 return false;
1028#else // !FULL_SYSTEM
1029 panic("fault (%d) detected @ PC %08p", inst_fault,
1030 head_inst->PC);
1031#endif // FULL_SYSTEM
1032 }
1033
1034 updateComInstStats(head_inst);
1035
1036 if (head_inst->traceData) {
1037 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1038 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1039 head_inst->traceData->finalize();
1040 head_inst->traceData = NULL;
1041 }
1042
1043 // Update the commit rename map
1044 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1045 renameMap[tid]->setEntry(head_inst->destRegIdx(i),
1046 head_inst->renamedDestRegIdx(i));
1047 }
1048
1049 // Finally clear the head ROB entry.
1050 rob->retireHead(tid);
1051
1052 // Return true to indicate that we have committed an instruction.
1053 return true;
1054}
1055
1056template <class Impl>
1057void
1058DefaultCommit<Impl>::getInsts()
1059{
1060 // Read any renamed instructions and place them into the ROB.
1061 int insts_to_process = min((int)renameWidth, fromRename->size);
1062
1063 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num)
1064 {
1065 DynInstPtr inst = fromRename->insts[inst_num];
1066 int tid = inst->threadNumber;
1067
1068 if (!inst->isSquashed() &&
1069 commitStatus[tid] != ROBSquashing) {
1070 changedROBNumEntries[tid] = true;
1071
1072 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1073 inst->readPC(), inst->seqNum, tid);
1074
1075 rob->insertInst(inst);
1076
1077 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1078
1079 youngestSeqNum[tid] = inst->seqNum;
1080 } else {
1081 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1082 "squashed, skipping.\n",
1083 inst->readPC(), inst->seqNum, tid);
1084 }
1085 }
1086}
1087
1088template <class Impl>
1089void
1090DefaultCommit<Impl>::markCompletedInsts()
1091{
1092 // Grab completed insts out of the IEW instruction queue, and mark
1093 // instructions completed within the ROB.
1094 for (int inst_num = 0;
1095 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1096 ++inst_num)
1097 {
1098 if (!fromIEW->insts[inst_num]->isSquashed()) {
1099 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1100 "within ROB.\n",
1101 fromIEW->insts[inst_num]->threadNumber,
1102 fromIEW->insts[inst_num]->readPC(),
1103 fromIEW->insts[inst_num]->seqNum);
1104
1105 // Mark the instruction as ready to commit.
1106 fromIEW->insts[inst_num]->setCanCommit();
1107 }
1108 }
1109}
1110
1111template <class Impl>
1112bool
1113DefaultCommit<Impl>::robDoneSquashing()
1114{
1115 list<unsigned>::iterator threads = (*activeThreads).begin();
1116
1117 while (threads != (*activeThreads).end()) {
1118 unsigned tid = *threads++;
1119
1120 if (!rob->isDoneSquashing(tid))
1121 return false;
1122 }
1123
1124 return true;
1125}
1126
1127template <class Impl>
1128void
1129DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1130{
1131 unsigned thread = inst->threadNumber;
1132
1133 //
1134 // Pick off the software prefetches
1135 //
1136#ifdef TARGET_ALPHA
1137 if (inst->isDataPrefetch()) {
1138 statComSwp[thread]++;
1139 } else {
1140 statComInst[thread]++;
1141 }
1142#else
1143 statComInst[thread]++;
1144#endif
1145
1146 //
1147 // Control Instructions
1148 //
1149 if (inst->isControl())
1150 statComBranches[thread]++;
1151
1152 //
1153 // Memory references
1154 //
1155 if (inst->isMemRef()) {
1156 statComRefs[thread]++;
1157
1158 if (inst->isLoad()) {
1159 statComLoads[thread]++;
1160 }
1161 }
1162
1163 if (inst->isMemBarrier()) {
1164 statComMembars[thread]++;
1165 }
1166}
1167
1168////////////////////////////////////////
1169// //
1170// SMT COMMIT POLICY MAINTAINED HERE //
1171// //
1172////////////////////////////////////////
1173template <class Impl>
1174int
1175DefaultCommit<Impl>::getCommittingThread()
1176{
1177 if (numThreads > 1) {
1178 switch (commitPolicy) {
1179
1180 case Aggressive:
1181 //If Policy is Aggressive, commit will call
1182 //this function multiple times per
1183 //cycle
1184 return oldestReady();
1185
1186 case RoundRobin:
1187 return roundRobin();
1188
1189 case OldestReady:
1190 return oldestReady();
1191
1192 default:
1193 return -1;
1194 }
1195 } else {
1196 int tid = (*activeThreads).front();
1197
1198 if (commitStatus[tid] == Running ||
1199 commitStatus[tid] == Idle ||
1200 commitStatus[tid] == FetchTrapPending) {
1201 return tid;
1202 } else {
1203 return -1;
1204 }
1205 }
1206}
1207
1208template<class Impl>
1209int
1210DefaultCommit<Impl>::roundRobin()
1211{
1212 list<unsigned>::iterator pri_iter = priority_list.begin();
1213 list<unsigned>::iterator end = priority_list.end();
1214
1215 while (pri_iter != end) {
1216 unsigned tid = *pri_iter;
1217
1218 if (commitStatus[tid] == Running ||
1219 commitStatus[tid] == Idle) {
1220
1221 if (rob->isHeadReady(tid)) {
1222 priority_list.erase(pri_iter);
1223 priority_list.push_back(tid);
1224
1225 return tid;
1226 }
1227 }
1228
1229 pri_iter++;
1230 }
1231
1232 return -1;
1233}
1234
1235template<class Impl>
1236int
1237DefaultCommit<Impl>::oldestReady()
1238{
1239 unsigned oldest = 0;
1240 bool first = true;
1241
1242 list<unsigned>::iterator threads = (*activeThreads).begin();
1243
1244 while (threads != (*activeThreads).end()) {
1245 unsigned tid = *threads++;
1246
1247 if (!rob->isEmpty(tid) &&
1248 (commitStatus[tid] == Running ||
1249 commitStatus[tid] == Idle ||
1250 commitStatus[tid] == FetchTrapPending)) {
1251
1252 if (rob->isHeadReady(tid)) {
1253
1254 DynInstPtr head_inst = rob->readHeadInst(tid);
1255
1256 if (first) {
1257 oldest = tid;
1258 first = false;
1259 } else if (head_inst->seqNum < oldest) {
1260 oldest = tid;
1261 }
1262 }
1263 }
1264 }
1265
1266 if (!first) {
1267 return oldest;
1268 } else {
1269 return -1;
1270 }
1271}