1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 46 unchanged lines hidden (view full) --- 55#include "cpu/base.hh" 56#include "cpu/exetrace.hh" 57#include "cpu/timebuf.hh" 58#include "debug/Activity.hh" 59#include "debug/Commit.hh" 60#include "debug/CommitRate.hh" 61#include "debug/Drain.hh" 62#include "debug/ExecFaulting.hh" |
63#include "debug/O3PipeView.hh" |
64#include "params/DerivO3CPU.hh" 65#include "sim/faults.hh" 66#include "sim/full_system.hh" 67 68using namespace std; 69 70template <class Impl> 71DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, --- 1191 unchanged lines hidden (view full) --- 1263 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 1264 head_inst->renamedDestRegIdx(i)); 1265 } 1266 1267 // Finally clear the head ROB entry. 1268 rob->retireHead(tid); 1269 1270#if TRACING_ON |
1271 if (DTRACE(O3PipeView)) { 1272 head_inst->commitTick = curTick() - head_inst->fetchTick; 1273 } |
1274#endif 1275 1276 // If this was a store, record it for this cycle. 1277 if (head_inst->isStore()) 1278 committedStores[tid] = true; 1279 1280 // Return true to indicate that we have committed an instruction. 1281 return true; --- 259 unchanged lines hidden --- |