1/* 2 * Copyright (c) 2010-2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 44 unchanged lines hidden (view full) --- 53#include "cpu/o3/thread_state.hh" 54#include "cpu/base.hh" 55#include "cpu/exetrace.hh" 56#include "cpu/timebuf.hh" 57#include "debug/Activity.hh" 58#include "debug/Commit.hh" 59#include "debug/CommitRate.hh" 60#include "debug/ExecFaulting.hh" |
61#include "params/DerivO3CPU.hh" 62#include "sim/faults.hh" 63#include "sim/full_system.hh" 64 65using namespace std; 66 67template <class Impl> 68DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, --- 1144 unchanged lines hidden (view full) --- 1213 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 1214 head_inst->renamedDestRegIdx(i)); 1215 } 1216 1217 // Finally clear the head ROB entry. 1218 rob->retireHead(tid); 1219 1220#if TRACING_ON |
1221 head_inst->commitTick = curTick() - head_inst->fetchTick; |
1222#endif 1223 1224 // If this was a store, record it for this cycle. 1225 if (head_inst->isStore()) 1226 committedStores[tid] = true; 1227 1228 // Return true to indicate that we have committed an instruction. 1229 return true; --- 259 unchanged lines hidden --- |